Turbulence models are reviewed and discussed with respect to their applicability in oscillating flow modeling. The Larn-Brernhorst form of the low-Reynolds number k-/spl epsilon/ turbulence model is chosen for oscilla...
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Turbulence models are reviewed and discussed with respect to their applicability in oscillating flow modeling. The Larn-Brernhorst form of the low-Reynolds number k-/spl epsilon/ turbulence model is chosen for oscillating flow modeling. Computations of oscillating flow in a finite pipe are compared with experimental data. While deficiencies of the turbulence model are identified, the overall agreement is shown to be very satisfactory. The instantaneous friction coefficients for fully developed flow are documented. The use of an effective Valensi number is proposed.
Cellular wave computers and cellular nonlinear network (CNN) technology are discussed in this paper. It is a system-on-chip (SoC) architecture with xK processors and sensor arrays. The architectural lessons from the t...
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Cellular wave computers and cellular nonlinear network (CNN) technology are discussed in this paper. It is a system-on-chip (SoC) architecture with xK processors and sensor arrays. The architectural lessons from the trends in manufacturing billion component devices when crossing the threshold of 100 nm feature size will determine the architecture, the elementary instructions, and the type of algorithms needed, hence also the complexity of the solution.
The paper proposes a new fault tolerant communication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed ...
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The paper proposes a new fault tolerant communication scheme for real-time operations and three new interconnection networks to construct a fault tolerant multi-processor system for pipeline processings. The proposed communication scheme using bank memory switching technique has an advantage to make a fault tolerant pipeline system so that it can detect any failure caused in a processing element of the system. In addition, it can overcome conventional problems caused in interconnection circuits to dataflow with one direction such as a pipeline processing.< >
The authors present a decentralized architecture for a multiprocessor database machine which supports multiple-user, online, very large relational database systems. A corresponding processor allocation strategy is pro...
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The authors present a decentralized architecture for a multiprocessor database machine which supports multiple-user, online, very large relational database systems. A corresponding processor allocation strategy is proposed which applies the dataflow technique to distribute processors across all nodes of the vertically layered query tree and to pipeline pages of intermediate relation between them. Simulations show that the query execution time is 20%-25% less than that in the DIRECT database machine. The time used to process the messages in the authors' database machine is almost 40% less than the time used in DIRECT. The simulation also indicated that the machine's structure is less sensitive to the I/O bound than the DIRECT machine.< >
The authors consider two implementation techniques for building a high-performance image-resampler VLSI chip. First, a two-level pipelined systolic array is designed for image resampling to give high parallelism in co...
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The authors consider two implementation techniques for building a high-performance image-resampler VLSI chip. First, a two-level pipelined systolic array is designed for image resampling to give high parallelism in computation and high feasibility for VLSI implementation. Second, a modified two-pass resampling scheme is used to decrease the amount of required storage and increase the concurrency between two resampling passes. With the two techniques, the system can provide a throughput of one pixel in a clock period smaller than that for an adder.< >
A method to determine the word length required by implementations of Digital Signal Processing (DSP) algorithms is presented. The method uses a C/C++ fixed-point simulation tool to model the impact of finite word leng...
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ISBN:
(纸本)0780366859
A method to determine the word length required by implementations of Digital Signal Processing (DSP) algorithms is presented. The method uses a C/C++ fixed-point simulation tool to model the impact of finite word length on overall accuracy. It finds a combination of quasi-optimum bit resolutions in arbitrary dataflow graphs by computing dissimilarities between fixed-point and floating-point simulation results. The selected algorithm minimizes these dissimilarities and finds a combination of word lengths that meets objectives specified by the user. This method is applicable to a wide range of DSP algorithms. It was tested on 2 benchmarks, the fifth order elliptic filter and the Inverse Discrete Cosine Transform (IDCT), and arrived to known optimum solutions.
A goal of the future air traffic control (ATC) system is to permit aircraft to fly according to their preferences (e.g., direct routes and optimum altitudes). Towards this goal, advanced automated en route ATC (AERA) ...
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A goal of the future air traffic control (ATC) system is to permit aircraft to fly according to their preferences (e.g., direct routes and optimum altitudes). Towards this goal, advanced automated en route ATC (AERA) concepts are currently in the research and development phase to provide a gradual evolution of ATC automation capabilities. The airborne flight management systems (FMSs) can provide accurate information on aircraft states needed to meet the automation objectives of advanced AERA concepts. The impact of user-preferred flight paths and altitudes on future ATC operations is analyzed. The results highlight potential fuel savings for the airspace users. Air/ground functional integration and information flow are discussed to minimize data ambiguities, and to reduce duplication of data in the airborne and ground computers. Computer/human interface requirements are also addressed. Key technical issues which must be addressed in order for the ground system to support flexible use of airspace, and increase system capacity in a diverse mix of aircraft operations are identified. The results presented show that FMS-equipped aircraft could realize significant fuel savings if permitted to fly preferred altitudes using step climbs.< >
The use of flow graphs to represent information flow distribution from data tables for intelligent data analysis was first proposed by Pawlak. This paper studies the representation of flow graphs by multiset decision ...
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The use of flow graphs to represent information flow distribution from data tables for intelligent data analysis was first proposed by Pawlak. This paper studies the representation of flow graphs by multiset decision tables. This representation is minimal. Inspired by the flow graphs, a new rule learning algorithm based on this representation is presented with examples. Two sets of rules are learned from certain examples and examples in the boundary set. Rules are characterized by Bayesian factors introduced by Pawlak.
An algorithmic program debugger for imperative languages is presented, with Pascal as an example case. This debugger extends the power of existing debuggers by providing an interactive debugging facility where errors ...
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An algorithmic program debugger for imperative languages is presented, with Pascal as an example case. This debugger extends the power of existing debuggers by providing an interactive debugging facility where errors can be localized semiautomatically. The debugger is activated on demand when the user discovers a symptom of an error as the result of some computation. This symptom presumably denotes a difference between the intended program behavior and the actual behavior. The proposed approach consists of three phases: program transformation, tracing, and debugging. The first phase transforms the source program into an internal representation which is appropriate, according to the Shapiro model, for algorithmic debugging. This phase produces an intermediate program which is free from side effects and loops. The program tracing phase generates trace information which builds an execution tree for the erroneous program. The debugging phase performs bug localization through a number of user interactions. This phase consists of pure algorithmic program debugging and program slicing.< >
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