A rotating magnetic field model of the axial induction motor is developed relating the geometric properties of the stator/rotor core. The main geometric dimensions of different type induction motors are compared using...
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A rotating magnetic field model of the axial induction motor is developed relating the geometric properties of the stator/rotor core. The main geometric dimensions of different type induction motors are compared using the field model formulas. An axial induction motor constant is derived from the output power formula. A new expression for the output power per unit volume is achieved by means of main dimensions and construction modification. A flowchart with stationary input data anticipates the assigned computed parameters of the axial induction motor.
We present a black-box active learning algorithm for inferring extended finite state machines (EFSM)s by dynamic black-box analysis. EFSMs can be used to model both dataflow and control behavior of software and hardw...
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We present a black-box active learning algorithm for inferring extended finite state machines (EFSM)s by dynamic black-box analysis. EFSMs can be used to model both dataflow and control behavior of software and hardware components. Different dialects of EFSMs are widely used in tools for model-based software development, verification, and testing. Our algorithm infers a class of EFSMs called register automata. Register automata have a finite control structure, extended with variables (registers), assignments, and guards. Our algorithm is parameterized on a particular theory, i.e., a set of operations and tests on the data domain that can be used in guards. Key to our learning technique is a novel learning model based on so-called tree queries. The learning algorithm uses tree queries to infer symbolic data constraints on parameters, e.g., sequence numbers, time stamps, identifiers, or even simple arithmetic. We describe sufficient conditions for the properties that the symbolic constraints provided by a tree query in general must have to be usable in our learning model. We also show that, under these conditions, our framework induces a generalization of the classical Nerode equivalence and canonical automata construction to the symbolic setting. We have evaluated our algorithm in a black-box scenario, where tree queries are realized through (black-box) testing. Our case studies include connection establishment in TCP and a priority queue from the Java Class Library.
作者:
Milutinovic, VeljkoFurht, BorkoObradovic, ZoranKorolija, NenadUniv Belgrade
Sch Elect Engn Dept Comp Engn & Informat Theory Bulevar Kralja Aleksandra 73 Belgrade 11120 Serbia Florida Atlantic Univ
Dept Comp & Elect Engn & Comp Sci Coll Engn & Comp Sci NSF UCRC CAKE 1 FAU Site777 Glades Rd Boca Raton FL 33431 USA Temple Univ
Ctr Data Analyt & Biomed Informat 1925 N 12th StSERC 035-02 Philadelphia PA 19122 USA Temple Univ
Comp & Informat Sci Dept 1925 N 12th StSERC 035-02 Philadelphia PA 19122 USA Temple Univ
Fox Sch Business Secondary Appointment Dept Stat 1925 N 12th StSERC 035-02 Philadelphia PA 19122 USA
The approach is based on hardware being configured for executing certain sets of instructions, where all instructions could be executed in parallel. Since high performance computing algorithms normally also include i...
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The approach is based on hardware being configured for executing certain sets of instructions, where all instructions could be executed in parallel. Since high performance computing algorithms normally also include instructions that are not repeatedly executed, dataflow computers are often combined with a control-flow processor. [...]in "Mining the IPTV Channel Change Event Stream to Discover Insight and Detect Ads" by M. Kren et al., it is analyzed how the data stream of the user-generated channel change events received from the entire IPTV network can be mined to obtain insights about the content.
The real-time interface requirements of a large hydroelectric power plant with its regional load dispatch office are described. The operative arrangement, interfacing functions, annual and weekly generation schedule, ...
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The real-time interface requirements of a large hydroelectric power plant with its regional load dispatch office are described. The operative arrangement, interfacing functions, annual and weekly generation schedule, and unit commitment are discussed. Automatic generation control, automatic bus voltage, river flow control, and operating conditions are discussed. All the functions were implemented for the Guri Hydroelectric Project in Venezuela, with total generating capacity of 10000 MW. Operation management functions are all handled by the Guri Computer Control System.< >
Existing methods for transient stability equivalents all lack a means of drawing a consistent boundary between the equivalized area and the area represented in detail. In most methods, it is assumed that the generator...
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Existing methods for transient stability equivalents all lack a means of drawing a consistent boundary between the equivalized area and the area represented in detail. In most methods, it is assumed that the generators equivalized are coherent. However, no simple method to identify them has been offered, which does not require a transient stability study of the entire system. A method using distance measures to draw boundaries and pattern recognition concepts to identify coherency is presented. Computation required is minimal. The method is incorporated in a computer program which is a useful tool for transient stability studies in power system planning.
Argus, a novel approach for detecting errors in simple processor cores, dynamically verifies the correctness of the four tasks performed by a Von Neumann core: control flow, dataflow, computation, and memory access. ...
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Argus, a novel approach for detecting errors in simple processor cores, dynamically verifies the correctness of the four tasks performed by a Von Neumann core: control flow, dataflow, computation, and memory access. Argus detects transient and permanent errors, with far lower impact on performance and chip area than previous techniques.
We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing dataflow is a major challenge as the s...
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We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing dataflow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem, There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat, The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system can be increased to more than 10 Gbps.
Role-Based Access Control (RBAC) is a widely used model for expressing access control policies. In large organizations, the RBAC policy may be collectively managed by many administrators. Administrative RBAC (ARBAC) m...
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Role-Based Access Control (RBAC) is a widely used model for expressing access control policies. In large organizations, the RBAC policy may be collectively managed by many administrators. Administrative RBAC (ARBAC) models express the authority of administrators, thereby specifying how an organization's RBAC policy may change. Changes by one administrator may interact in unintended ways with changes by other administrators. Consequently, the effect of an ARBAC policy is hard to understand by simple inspection. In this paper, we consider the problem of analyzing ARBAC policies. Specifically, we consider reachability properties (e.g., whether a user can eventually be assigned to a role by a group of administrators), availability properties (e.g., whether a user cannot be removed from a role by a group of administrators), containment properties (e.g., every member of one role is also a member of another role) satisfied by a policy, and information flow properties. We show that reachability analysis for ARBAC is PSPACE-complete. We also give algorithms and complexity results for reachability and related analysis problems for several categories of ARBAC policies, defined by simple restrictions on the policy language. Some of these results are based on the connection we establish between security policy analysis and planning problems in Artificial Intelligence. (C) 2011 Elsevier B.V. All rights reserved.
The design of a multimicroprocessor system intended for a class of real-time processing applications is discussed. The applications considered require the computation of a subset of an N-input Fourier transform under ...
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The design of a multimicroprocessor system intended for a class of real-time processing applications is discussed. The applications considered require the computation of a subset of an N-input Fourier transform under the assumption of a serial data input. The suitability of two different algorithms and the corresponding parallel architectures is analyzed and compared. More specifically, we compare the computation of the FFT algorithms on an SIMD (single instruction multiple data) machine to the implementation of the DFT algorithm on an MISD (multiple instruction single data) machine. Our results indicate that the latter is better suited for the targeted applications. An actual operational MISD computer, implemented with off-the-shelf microprocessors intended for one of the targeted applications, is described.
A new method for parallel decomposition of a sparse matrix is presented. The architectural model is a multiprocessor hypercube. The development of this method is based on two concepts, namely, the dataflow computer a...
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A new method for parallel decomposition of a sparse matrix is presented. The architectural model is a multiprocessor hypercube. The development of this method is based on two concepts, namely, the dataflow computer and the path graph. Also, a sparse-oriented operational sequence matrix C is used to store and manipulate the dataflow. The C matrix presents the time units and the sequence of all divide and update operations in the LU decomposition. From the C matrix, the minimal completion time, the critical path, and the scheduling of the processors for the LU decomposition can be determined. The proposed method recognizes the fact that the operating times units among division, multiplication, and subtraction in the processor are not the same. Also, communication overhead is included. A number of power systems have been implemented and a number of conditions have been simulated to evaluate the performance of the proposed method. The results are presented and discussed.< >
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