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检索条件"主题词=Data Flow Computing"

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Designing systems for highly parallel and distributed computing

Designing systems for highly parallel and distributed comput...

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Annual Hawaii International Conference on System Sciences (HICSS)

作者： N. Vidovic D.F. Vrsalovic L. Budin School of Computer Science Carnegie Mellon University USA Ready Systems Sunnyvale CA USA Elektrotehnicki Fakultet U Zagrebu University of Zagreb Yugoslavia

The parallel computational model with data flow sequencing is introduced. Description of the basic principles and features of mpDF, a massively parallel architecture, based on the dataflow operational model and RISC organizational principles is presented. The analytical performance model is developed to evaluate proposed architectural solution for distributed/parallel computing based on data flow sequencing of instructions. Algorithmic performance model is extended to include characterization of the parallel programs in terms of the average parallelism. Model is solved for number of different workloads. The values of the basic architectural characteristics are analyzed showing that architecture is well balanced providing consistent performance made for wide rage of parallel applications.< >

关键词： Distributed computing Performance analysis Parallel processing Concurrent computing data flow computing Computational modeling Parallel architectures Reduced instruction set computing Analytical models Computer architecture

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computing lower bounds on functional units before scheduling

Computing lower bounds on functional units before scheduling

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International Symposium on High-Level Synthesis

作者： S. Chaudhuri R.A. Walker Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy NY USA Department of Computer Science Rensselaer Polytechnic Institute Troy NY USA

Presents a new algorithm for computing lower bounds on the number of functional units (FUs) required to schedule a data flow graph in a specified number of control steps. We use a formal approach to compute the bounds that can be proven to be tighter than those produced by existing methods, and that considers the interdependencies of the bounds on the different FU-types. This quick, yet accurate estimation of the number of FUs is used to generate resource constraints for a design, and thus reduce the design space.< >

关键词： Processor scheduling data flow computing Scheduling algorithm flow graphs Algorithm design and analysis Strain control Heuristic algorithms Design engineering Systems engineering and theory Computer science

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SIF: Overcoming the limitations of SIMD devices via implicit permutation

SIF: Overcoming the limitations of SIMD devices via implicit...

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IEEE Symposium on High-Performance Computer Architecture

作者： Libo Huang Li Shen Zhiying Wang Wei Shi Nong Xiao Sheng Ma School of Computer National University of Defense Technology China

ISBN: (纸本)9781424456581

SIMD devices have gained widespread acceptance in modern microprocessor designs for their superior performance for multimedia applications. However, there are three remaining limitations to the efficient utilization of SIMD devices in general-purpose computer systems: memory alignment, data reorganization and control flow. This paper presents SIF, an efficient SIMD interface framework that addresses these three shortcomings without modifying existing ISA. It is designed around a permutation vector register file (PVRF) and it adds new extended instructions to set internal permutation state in SIMD datapath rather than putting the permutation state setting bits in every instruction. The implicit permutation capability provided by PVRF results in zero overhead, which frees the handling of three limitations by using permutation instructions. To further reduce the state setting instructions in SIMD datapath, a technique that moves the workloads from SIMD pipeline into scalar pipeline is also introduced. With the help of proposed compilation algorithm, SIF can efficiently transform regular SIMD codes into SIF codes which make it easily integrated in all existing SIMD devices. We implemented these techniques in a vectorizing compiler and experimental results show that most of the permutation overhead instructions can be eliminated and distinct performance speedup can be achieved, which is 37% higher than current SIMD techniques on average.

关键词： Pipelines Hardware Virtual colonoscopy Microprocessors Application software data flow computing Control systems Instruction sets Registers Process design

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A VME barrel shifter system for event reconstruction for up to 3 Gbps signal trains

A VME barrel shifter system for event reconstruction for up ...

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IEEE Symposium on Nuclear Science (NSS/MIC)

作者： O. Sasaki M. Nomachi T.K. Ohska H. Fujii National Laboratory for High Energy Physics (KEK) Tsukuba Ibaraki Japan

A VME barrel shifter system for event reconstruction was developed for the SDC (Solenoidal Detector Collaboration) experiment. A special semi-custom switch IC was also developed for it. The system takes in fragments of a physical event through its inputs, combines and reorganizes them, and produces a complete data set of the event from one of its outputs. The complete output data set for successive events will be delivered to waiting computers at its outputs. Up to 3-Gb/s signal trains can be fed through the switch unit. This system is VME 6U compatible and the switching can be controlled by a commercially available VME module. The building blocks of this barrel shifter system are switch modules, O/E and E/O converter modules, and a dedicated crate. The switch modules are a dual-4*4/quad-2*2 unit and an 8*8 unit; they can be combined to deal with a very large number of input/output channels.< >

关键词： Switches data flow computing Distributed computing Physics computing Shape control Laboratories Control systems Parallel processing Event detection Detectors

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Design and Implementation of an All-Analog Fast-Fourier Transform Processor

Design and Implementation of an All-Analog Fast-Fourier Tran...

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50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'07), vol.3

作者： Keith Boyle Pat Mercier Nima Sadeghi Vincent Gaudet Christian Schlegel Chris Winstead Manohar Kashyap Department of Electrical and Computer Engineering University of Alberta Edmonton AB Canada Department of Electrical and Computer Engineering Utah State University Logan UT USA

The implementation of a 64-symbol analog, current-mode FFT processor is discussed. An analog FFT would be suitable for combination with an Analog Decoder in the making of an all-analog communication front-end for OFDM systems. Here the FFT is implemented using a butterfly diagram as the system block diagram;each node in the diagram is implemented using analog circuits. Implementation details, including consideration of the effect of approximation errors and the implementation of a test chip, are discussed.

关键词： Fast Fourier transforms Wires OFDM Iterative decoding flow graphs data flow computing Testing Feeds Mirrors Analog circuits

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Optimal code size reduction for software-pipelined and unfolded loops

Optimal code size reduction for software-pipelined and unfol...

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International Symposium on System Synthesis

作者： Qingfeng Zhuge Bin Xiao Zili Shao E.H.-M. Sha Chantana Chantrapornchai Department of Computer Science University of Texas Dallas Richardson TX USA Faculty of Science Silpakorn University Nakhon Pathom Thailand

ISBN: (纸本)1581135769

Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application significantly. For most DSP systems with limited memory resources, code size becomes one of the most critical concerns for the high-performance applications. In this paper, we present the code size reduction theory based on retiming and unfolding concepts. We propose a code size reduction framework to achieve the optimal code size of software-pipelined and unfolded loops by using conditional registers. The experimental results on several well-known benchmarks show the effectiveness of our code size reduction technique in controlling the code size of optimized loops.

关键词： flow graphs data flow computing Processor scheduling Pipeline processing Delay effects Law Legal factors Application software Constraint optimization Memory management

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dataflow frequency analysis based on whole program paths

Dataflow frequency analysis based on whole program paths

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International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： B. Scholz E. Mehofer Institute of Computer Languages University of Technology Vienna Vienna Austria Institute for Software Science University of Technology Vienna Vienna Austria

Efficient use of machine resources in high-performance computer systems requires highly optimizing compilers with sophisticated analyses. Static analysis often fails to identify frequently executed portions of a program which are the places where optimizations achieve the greatest benefit. This paper introduces a novel data flow frequency analysis framework that computes the frequency with which a data flow fact will hold at some program point based on profiling information. Several approaches which approximate the frequencies based on k-edge profiling have been presented. However, no feasible approach for obtaining the accurate solution exists so far. Recently, efficient techniques for recording whole program paths (WPPs) have been developed. Our approach for computing data flow frequencies results in an accurate solution and utilizes WPPs to obtain the solution in reasonable time. In our experiments we show that the execution time of WPP-based frequency analysis is in case of the SPEC benchmark suite only a fraction of the overall compilation time.

关键词： Frequency data analysis data flow computing Instruments Information analysis Optimizing compilers Feedback History Open loop systems Computer languages

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Centralized versus Decentralized Conversation-based Orchestrations

Centralized versus Decentralized Conversation-based Orchestr...

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IEEE International Conference on e-Commerce Technology (CEC)

作者： Ustun Yildiz Claude Godart INRIA/LORIA Vandoeuvre-les-Nancy France CRP-Gabriel Lippmann Belvaux Luxembourg

There has been a great deal of interest in recent years in the use of service oriented approach and relevant standards to implement business processes. Following the concepts of workflow-based process management, the major focus has been on service composition. Not surprisingly, this default composition approach suffers from the limitations of centralized workflow management. It is well recognized that a decentralized execution setting where composed services can establish P2P interactions, is central to the management of a wide range of ubiquitous, mobile, large-scale and secure business processes. A natural way to enable the decentralized execution is to implement the relevant distributed cooperating processes of a centralized process on composed services. In this way, composed services can establish P2P interactions following the semantics of their processes. In this paper, we present a generic approach that enables decentralized executions with such cooperating processes. Precisely, we present our method that derives the latter. We focus on the sophisticated control/data flow and conversational aspects that run counter to naive intuition, most of which, we explain using deeper analysis of the algorithms and data structures that we employed.

关键词： Counting circuits Standards organizations Centralized control Large-scale systems Algorithm design and analysis data structures data flow computing Standardization Art Context-aware services

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Performance analysis of packet switching interconnection networks with finite buffers

Performance analysis of packet switching interconnection net...

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EUROMICRO Conference

作者： A. Tentov A. Grnarov Computer Science Department Electrical Engineering University Saint Kiril i Metodij Macedonia

In this paper, a mathematical method for analysis of synchronous packet-switching interconnection networks with finite buffering capacity at the output of switching elements is presented. The proposed mathematical method is general in that it analyzed interconnection networks under uniform and nonuniform traffic with blocking. The existing methods for analysis of buffered interconnection networks have assumed either single or infinite buffers at each input (or output) port of a switch, as well as uniform traffic pattern of the networks. Firstly, in the paper a general model of synchronous buffered switching element, using output buffering, under assumption of finite buffer size for a very general class of traffic, is presented. Traffic can be uniform or nonuniform. It is assumed that the subsequent stages of the network are nearly independent and a model is extended for entire network under this assumption. Analytical results obtained with proposed model are then compared with each other and it is shown that the proposed mathematical method is more general then the known models of interconnection networks.

关键词： Performance analysis Packet switching Multiprocessor interconnection networks Switches Telecommunication traffic Traffic control Asynchronous transfer mode Concurrent computing data flow computing Distributed computing

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A Structural Object Programming Model, Architecture, Chip and Tools for Reconfigurable computing

A Structural Object Programming Model, Architecture, Chip an...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Michael Butts Anthony Mark Jones Paul Wasson Ambric Inc. Beaverton OR USA

A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using software languages and methodologies. Its objectives are massive performance, long-term scalability, and easy development. In our structural object programming model, objects are strictly encapsulated software programs running concurrently on an asynchronous array of processors and memories. They exchange data and control through a structure of self-synchronizing asynchronous channels. Objects are combined hierarchically to create new objects, connected through the common channel interface. The first chip is a 130nm ASIC with 360 32-bit processors, 360 1KB RAM banks with access engines, and a configurable word-wide channel interconnect. Applications written in Java and block diagrams compile in one minute. Sub-millisecond runtime reconfiguration is inherent.

关键词： Computer architecture Hardware Field programmable gate arrays Application software Power engineering computing Programming profession data flow computing Silicon Scalability Java

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