We describe here the FB [ 1 ] double port buffer memory developped at the LPNHE of the University Paris VI. Its purposes are to make available same features useful in the High Energy environment, to reduce, for a give...
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We describe here the FB [ 1 ] double port buffer memory developped at the LPNHE of the University Paris VI. Its purposes are to make available same features useful in the High Energy environment, to reduce, for a given amount of memory, the dead time data collection in a large size (in term of read-out channels) High Energy experiment and to get a buffer of memory as cheap and reliable as possible. The FB protocol, on the crate and cable side, is exploited using the coupler on 4 PAL's developped by G. Fremont [ 2 ] and E. Sanchis. The data-Space is divided in 4 independent smaller blocks in a way such that a block can be accessed from a port while a different block is accessed from the other port. The two ports are : A, the FB crate port and B, the FB cable port. The buffer works as a rotary FIFO, looping over the 4 blocks of memory, but allowing for any random access. A mechanism is implemented on the board in order to be able to link different modules placed everywhere. If there are m modules, the looping will be around m*4 memory blocks. A multi event function is implemented on the board. HFB is quiped of two NTA for the dataSpace on the port "A", and a flag to choose between them, to allow for a FB spying of data during the DAS dead time.
We look at a very simple model of parallel computation and study the question of how restricting the flow of data to be one-way compares with two-way flow. A one-way linear iterative array (1LIA) is a finite one-dimen...
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We look at a very simple model of parallel computation and study the question of how restricting the flow of data to be one-way compares with two-way flow. A one-way linear iterative array (1LIA) is a finite one-dimensional array of identical finite-state machines (cells) in which information is allowed to move only in one direction- from left to right. For inputs of length n, the array uses n cells which are initially set to the quiescent state. The serial input, which is applied to the leftmost cell, is accepted if the rightmost cell ever enters an accepting state. We give results which show that 1LIA's are surprisingly very powerful in that they can accept languages which seemingly require two-way communication.
This paper describes a set of techniques for the synthesis of pipelined data paths, and presents Sehwa, a program which performs such synthesis. The task includes the generation of data paths from a dataflow graph al...
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This paper describes a set of techniques for the synthesis of pipelined data paths, and presents Sehwa, a program which performs such synthesis. The task includes the generation of data paths from a dataflow graph along with a clocking scheme which overlaps execution of multiple tasks. Some examples which Sehwa has designed are given. Sehwa can find the minimum cost design, the highest performance design, and other designs between these two in the design space. We believe Sehwa to be the first pipelined synthesis program published in the open literature. Sehwa is written in Franz LISP, and executes within minutes for problems of practical size on a VAX 11/750.
To effectively manage the development, acquisition, and operation of the NGWLMS, a special purpose management information system (MIS) was designed featuring: project scheduling and cost reporting, item tracking, and ...
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To effectively manage the development, acquisition, and operation of the NGWLMS, a special purpose management information system (MIS) was designed featuring: project scheduling and cost reporting, item tracking, and document comparison. The NGWLMS project was structured as a six-level, parent/subtask hierarchy with no restrictions on interlevel predecessor task relationships; two categories of task schedules and cost data are maintained--planned and current. Several databases are used to track items, such as equipment, facilities and spare parts. A semi-automated method is provided to aid reviewers in comparing parallel documents, such as proposals vs, specifications or test results vs. test plans. The MIS was written in Ashton-Tate's dBASE III and Framework software packages, and operates on an IBM PC/AT personal computer.
Within the context of flow control problems in data communication networks, we consider decentralized algorithms which optimize a criterion reflecting the trade-off between the throughput and the total delay in a virt...
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Within the context of flow control problems in data communication networks, we consider decentralized algorithms which optimize a criterion reflecting the trade-off between the throughput and the total delay in a virtual circuit. We show that the "greedy" algorithm which provides individually optimum solutions for the users converges when the criterion is the power of the virtual circuit. We also present an algorithm executed using decentralized information which converges to a set of Pareto-optimum message rates among the users. Both of the algorithms make use of the local information available to end users and no exchange of information is needed.
Multiply and accumulate are the two basic operations for FFT and digital filtering algorithms. In high-speed applications, the multiplier is crucial to the performance. The multiplier requires either large chip area i...
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Multiply and accumulate are the two basic operations for FFT and digital filtering algorithms. In high-speed applications, the multiplier is crucial to the performance. The multiplier requires either large chip area if parallel implementation is used or large amount of time if serial architecture is used. In this paper, the design of basic FFT arithmetic element and FIR filters using barrel shifters and accumulators (BSAC) to perform the multiplications is proposed and studied. The resulting architecture is completely programmable and allows the use of variable number of basic cells for each coefficient. The throughput rate of such an architecture is determined only by the delay in a single cell and hence can be of the order of 100 MHz or higher.
This paper discusses an environment for configuration, programming, and control of robot workcells. The controller is intended to support research in automation programming and motion control, and to provide a vehicle...
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This paper discusses an environment for configuration, programming, and control of robot workcells. The controller is intended to support research in automation programming and motion control, and to provide a vehicle for conveniently integrating new sensors and other devices into a workcell in a useful way. The system consists of an interactive Programming System connected through a shared memory to a multiple-processor Real Time System that performs time-critical operations. The Programming System executes programs written in an enhanced version of AML and transmits high level commands, called verbs, to the Real Time System for execution. Verbs may either be simple, consisting essentially of a process specification and termination conditions, or they may be compositions of other verbs. The processes themselves are specified in terms of lower level entities called real time application subroutines, state vector variables, and dataflow graphs which describe computations to be performed in the Real Time System.
The real discrete Fourier transform (RDFT) corresponds to the Fourier series for sampled periodic signals with sampled periodic frequency responses just as discrete Fourier transform (DFT) corresponds to the complex F...
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The real discrete Fourier transform (RDFT) corresponds to the Fourier series for sampled periodic signals with sampled periodic frequency responses just as discrete Fourier transform (DFT) corresponds to the complex Fourier series for the same type of signals. RDFT has better performance than DFT in data compression and filtering for all signals in the sense that Pearl's measure for RDFT is less than Pearl's measure for DFT by an amount ΔW. RDFT also has better performance than DFT in the computation of real convolution because of the reduced number of operations, and the fact that forward and inverse transforms can be implemented with the same signal flowgraph, thereby facilitating hardware and software design.
Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at vi...
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Real-time image processing in an application environment needs a set of low-cost implementations of various algorithms. This paper presents a one chip VLSI median filter based on a systolic processor and working at video rate. It includes its own memory and can be used without any image memory for on-line processing. The architectural choices have made it possible to design a small size chip with a high performance level.
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