A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using ...
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A new platform for reconfigurable computing has an object-based programming model, with architecture, silicon and tools designed to faithfully realize this model. The platform is aimed at application developers using software languages and methodologies. Its objectives are massive performance, long-term scalability, and easy development. In our structural object programming model, objects are strictly encapsulated software programs running concurrently on an asynchronous array of processors and memories. They exchange data and control through a structure of self-synchronizing asynchronous channels. Objects are combined hierarchically to create new objects, connected through the common channel interface. The first chip is a 130nm ASIC with 360 32-bit processors, 360 1KB RAM banks with access engines, and a configurable word-wide channel interconnect. Applications written in Java and block diagrams compile in one minute. Sub-millisecond runtime reconfiguration is inherent.
CODACS (configurable dataflowcomputing system) project target is to realize a high performance reconfigurable computing system demonstrator able to directly execute in hardware dataflow graphs generated compiling pro...
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CODACS (configurable dataflowcomputing system) project target is to realize a high performance reconfigurable computing system demonstrator able to directly execute in hardware dataflow graphs generated compiling programs written in CHIARA language. In this paper we present the reconfigurable environment and how it executes chunks of a dataflow graph produced by CHIARA compiler. This environment, which is transparent to the user, consists of a set of processing elements called platform-processors. Each platform-processor, based on the static dataflow model, is created by a set of identical computing units (CUs) and a reconfigurable interconnect. While CUs execute any elementary operator of the language, implement the actor described in the homogeneous high-level dataflow system model, and act according to the model firing rules, the reconfigurable interconnect allows to execute dataflow graphs directly in hardware. Furthermore, thanks to the homogeneous actor I/O conditions (one output and two input links) of the model, a one-to-one mapping between dataflow actors of the model and CUs occurs in a straightforward manner. Consequently, the platform-processor executes dataflow graphs without: a) using memory to store partial results when data tokens flow from a CU to another; b) generating control tokens during this computation so that graph executions can happen in a completely asynchronous manner. However, synchronizing CUs activities, the platform-processor architecture also allows the execution of pipeline operations.
A graphical behavioral description method using Control-dataflow Graphs (CDFG) in VisualVHDL is introduced, and the algorithm generating VHDL text file from CDFG is described. It involves the application of visual la...
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ISBN:
(纸本)0780330625
A graphical behavioral description method using Control-dataflow Graphs (CDFG) in VisualVHDL is introduced, and the algorithm generating VHDL text file from CDFG is described. It involves the application of visual language in hardware design field.
We present a scheduling protocol, called time-shift scheduling, to forward data packets from multiple input flows to a single output channel. Each input flow is guaranteed a predetermined forwarding rate and an upper ...
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We present a scheduling protocol, called time-shift scheduling, to forward data packets from multiple input flows to a single output channel. Each input flow is guaranteed a predetermined forwarding rate and an upper bound on packet delay. The protocol is an improvement over existing protocols because it satisfies the properties of low delay, fairness, and efficiency, while existing protocols fail to satisfy at least one of these properties. In time-shift scheduling, each flow is assigned an increasing timestamp, and the packet chosen for transmission is taken from the flow with the least timestamp. The protocol features the novel technique of time shifting, in which the scheduler's real-time clock is adjusted to prevent flow timestamps from increasing faster than the real-time clock. This bounds the difference between any pair of flow timestamps, thus ensuring the fair scheduling of flows.
Modularization and abstraction are the keys to practical verification and analysis of large and complex systems. We present in an incremental methodology for the automatic analysis and verification of concurrent softw...
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Modularization and abstraction are the keys to practical verification and analysis of large and complex systems. We present in an incremental methodology for the automatic analysis and verification of concurrent software systems. Our methodology is based on the theory of abstract interpretation. We first propose a compositional dataflow analysis algorithm that computes invariants of concurrent systems by composing invariants generated separately for each component. We present a novel compositional rule allowing us to obtain invariants of the whole system as conjunctions of local invariants of each component. We also show how the generated invariants are used to construct, almost for free, finite state abstractions of the original system that preserve safety properties. This reduces dramatically the cost of computing such abstractions as reported in previous work. We finally give a novel refinement algorithm that refines the constructed abstraction until the property of interest is proved or a counterexample is exhibited. Our methodology is implemented in a framework that combines deductive methods supported by theorem proving techniques and algorithmic methods supported by model checking and abstract interpretation techniques.
In view of defects of tradition chips used for conference systems, such as poor performance and higher prices, this paper proposes the technical solution to use DSP technology to design and realize the multi-party con...
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In view of defects of tradition chips used for conference systems, such as poor performance and higher prices, this paper proposes the technical solution to use DSP technology to design and realize the multi-party conference system, and describes detailed designs and specified realization methods. With stable performance and requiring much lower costs, the product is now being extensively applied in Chinese railway and military systems and achieving favorable economic and social benefits.
The detection of various dependencies that exist among the definitions and uses of variables in a program is necessary in many language-processing tools. The computation of definition-use dependencies that reach acros...
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The detection of various dependencies that exist among the definitions and uses of variables in a program is necessary in many language-processing tools. The computation of definition-use dependencies that reach across procedure boundaries is considered. In particular, efficient techniques for computing interprocedural definition-use and use-definition chains and for incrementally updating the chains when a change is made in a procedure are presented. Intraprocedural definition and use information for each procedure is first abstracted and used to construct an interprocedural flow graph. The intraprocedural information is then propagated in two phases throughout the interprocedural flow graph to obtain the complete set of interprocedural reaching definitions and reachable uses. Interprocedural definition-use and use-definition chains are computed from this reaching information. The technique handles the interprocedural effects of the flow of data caused by both reference parameters and global variables, as well as supports separate compilation even in the presence of recursion. The technique has been implemented using a Sun 3/50 workstation and incorporated into an interprocedural dataflow tester.< >
In addition to the statistical evaluation of measurements made on physiological processes, there is an increasing demand for the theoretical system description in terms of cause-effect relationship as well as the quan...
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In addition to the statistical evaluation of measurements made on physiological processes, there is an increasing demand for the theoretical system description in terms of cause-effect relationship as well as the quantitative determination of such processes. The first part of this article deals with identification while the second part describes a new event recognition method.
The status and flow of land utilization database is studied and optimized, and an improved algorithm is proposed in the paper. Intelligent method is used in supervising and evaluating the result of the database for th...
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The status and flow of land utilization database is studied and optimized, and an improved algorithm is proposed in the paper. Intelligent method is used in supervising and evaluating the result of the database for the first time, such as the elements of polygon area, district, linear object, designing and realizing the corresponding mathematical models and the intelligent analysis procedures to ensure the quality of database and the fast application of database.
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