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检索条件"主题词=Data Flow Computing"

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MavEStream: Synergistic Integration of Stream and Event Processing

MavEStream: Synergistic Integration of Stream and Event Proc...

引用

International Conference on Digital Telecommunications (ICDT)

作者： Qingchun Jiang Raman Adaikkalavan Sharma Chakravarthy ANTs Software Inc. Burlingame CA USA CIS Department IU South Bend USA CSE Department UT Arlington USA CSE Department UT Arlington

Although research seems to address event and stream data processing as two separate topics, there are a number of similarities between them. For many advanced stream applications, both event and rule processing are needed and are not currently well-supported. Extant event processing systems concentrate primarily on complex events and rules and stream processing systems concentrate on stream operators, scheduling, and quality of service issues. Synergistic integration of these models will be better than the sum of its parts. We propose an integrated model to combine the capabilities of both models for applications that need both of them. Specifically, we introduced a number of enhancements, including stream modifiers, semantic windows, event generators, and enhanced event and rule specifications, to couple two models seamlessly. We prototype our integrated system using the stream processing system (MavStream) with the event processing system (Snoop and Sentinel) and discuss the design and implementation issues of our prototype.

关键词： Computational modeling data processing Quality of service Prototypes Application software data flow computing flow graphs Event detection Context modeling Computational Intelligence Society

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Bounding algorithms for design space exploration

Bounding algorithms for design space exploration

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Great Lakes Symposium on VLSI

作者： S. Chaudhuri R.A. Walker Magrnu Design Automation San Antonio CA USA Kent University Kent OH USA

This paper describes several new algorithms for computing lower bounds on the length of the schedule and the number of functional units in high-level synthesis.

关键词： Algorithm design and analysis Space exploration Processor scheduling High level synthesis Delay data flow computing Scheduling algorithm Clocks Upper bound flow graphs

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Speeding up NGB with distributed file streaming framework 06

Speeding up NGB with distributed file streaming framework

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Bingchen Li Kang Chen Zhiteng Huang H.L. Rajic R.H. Kuhn Intel China Research Center Limited Beijing China Software Products Division Intel KSL Urbana-Champaign IL USA

ISBN: (纸本)9781424400546

Grid computing provides a very rich environment for scientific calculations. In addition to the challenges it provides, it also offers new opportunities for optimization. In this paper we have utilized DFS (distributed file streaming) framework to speed up NAS grid benchmark workflows. By studying I/O patterns of NGB codes we have identified program locations where it is possible to overlap computation and data workflow phases. By integrating DFS into NGB, we demonstrate a useful method of improving overall workflow efficiency by streaming the output of the current process to make an input of the following stage, reducing a workflow to a series of distributed producer consumer stages. DFS framework eliminates file transfers and in the process makes process scheduling more efficient, leading to overall performance improvements in the turnaround time for HC (helical chain) data flow graph under Globus grid environment with the embedded DFS over the original version of the benchmark

关键词： flow graphs data flow computing Grid computing Computational fluid dynamics Distributed computing Encapsulation Processor scheduling Bandwidth Application software Hardware

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Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions

Incorporating speculative execution into scheduling of contr...

引用

Design Automation Conference

作者： G. Lakshminarayana A. Raghunathan N.K. Jha C&C Research Laboratories NEC USA Inc. Princeton NJ USA Department of Electrical Engineering Princeton University Princeton NJ USA

Speculative execution refers to the execution of parts of a computation before the execution of the conditional operations that decide whether it needs to be executed. It has been shown to be a promising technique for eliminating performance bottlenecks imposed by control flow in hardware and software implementations alike. In this paper, we present techniques to incorporate speculative execution in a fine-grained manner into scheduling of control-how intensive behavioral descriptions. We demonstrate that failing to take into account information such as resource constraints and branch probabilities can lead to significantly sub-optimal performance. We also demonstrate that it may be necessary to speculate simultaneously along multiple paths, subject to resource constraints, in order to minimize the delay overheads incurred when prediction errors occur. Experimental results on several benchmarks show that our speculative scheduling algorithm can result in significant (up to seven-fold) improvements in performance (measured in terms of the average number of clock cycles) as compared to scheduling without speculative execution. Also, the best and worst case execution times for the speculatively performed schedules are the same as or better than the corresponding values for the schedules obtained without speculative execution.

关键词： High level synthesis Permission Clocks Laboratories Processor scheduling data flow computing Hardware Software performance Delay Scheduling algorithm

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Embedded intelligent SRAM 03

Embedded intelligent SRAM

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Design Automation Conference

作者： P. Jain G.E. Suh S. Devadas Laboratory for Computer Science Massachusetts Institute of Technology Cambridge MA USA

ISBN: (纸本)9781581136883

Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that consists of a small computation unit with an accumulator that is placed near the on-chip SRAM. The computation unit can perform operations on two words from the same SRAM row or on one word from the SRAM and the other from the accumulator. This ISRAM enhancement requires only a few additional instructions to support the computation unit. We present a computation partitioning algorithm that assigns the computations to the processor or to the new computation unit for a given data flow graph of a program. Performance improvement results from the reduction in the number of accesses to the SRAM, the number of instructions, and the number of pipeline stalls compared to the same operations in the processor. Experimental results on various benchmarks show up to 1.46X speedup with our enhancement.

关键词： Random access memory data flow computing Embedded system Reduced instruction set computing Embedded computing System-on-a-chip Computer aided instruction Partitioning algorithms flow graphs Pipelines

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Soylent Grid: it's Made of People

Soylent Grid: it's Made of People

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International Conference on Computer Vision (ICCV)

作者： Stephan Steinbach Vincent Rabaud Serge Belongie Calit University of California San Diego La Jolla CA USA Department of Computer Science and Engineering University of California San Diego La Jolla CA USA

The ground truth labeling of an image dataset is a task that often requires a large amount of human time and labor. We present an infrastructure for distributed human labeling that can exploit the modularity of common vision problems involving segmentation and recognition. We present the different elements of this infrastructure in detail, in particular the different vision human computational tasks (HCTs) and machine computable tasks (MCTs). We also discuss the impact of such a system on Internet security vs. the current state of the art. Finally, we present our prototype implementation of such a system, named soylent grid, on typical problems.

关键词： Labeling Humans Optical character recognition software Computer vision Image segmentation Detectors Testing Distributed computing Computer networks data flow computing

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Semantics of optimistic computation

Semantics of optimistic computation

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International Conference on Distributed computing Systems

作者： R. Bubenik W. Zwaenepoel Department of Computer Sciences Washington University Saint Louis MI USA Department of Computer Sciences Rice University Houston TX USA

The derivation of a semantically equivalent optimistic computation from a pessimistic computation by application-independent transformations is discussed. Computations are modeled by program dependence graphs (PDGS). The semantics of a computation is defined by a mapping from an initial state to a final state and is realized by a graph rewriting system. Semantics-preserving transformations are applied to PDGS of the pessimistic computation to produce an optimistic version. The transformations result from guessing data values and control flow decisions in the computation. The transformations are used to derive an optimistic version of fault tolerance based on message logging and checkpointing. The transformations yield an optimistic version similar to optimistic fault-tolerance algorithms reported in the literature, although additional application-dependent transformations are necessary to produce a realistic optimistic implementation.< >

关键词： Fault tolerance Computational modeling Checkpointing Computer science data flow computing Constraint optimization Concurrent computing Parallel processing Performance loss Performance gain

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Resource constrained algebraic transformation for loop pipelining 96

Resource constrained algebraic transformation for loop pipel...

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Great Lakes Symposium on VLSI

作者： Jian-Feng Shi Liang-Fang Chao Department of Electrical and Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)0818675020

Loop pipelining can be applied to a cyclic data-flow graph to reduce the iteration bound, which is the maximum computation-time-to-delay ratio among all the cycles in the data flow graph. Algebraic transformations can reduce the iteration bound substantially. However, resource constrained algebraic transformations for loop pipelining remains a hard problem because of the inherent nature of loop pipelining. In this paper, we propose a new method based on distribution graphs to solve this problem. A novel algorithm for algebraic transformation with resource constraints is provided, which works for non-pipelined schedules as well. Experimental results show that our algorithm is promising.

关键词： Pipeline processing Delay Iterative algorithms Processor scheduling Scheduling algorithm data flow computing Force control Chaos data engineering flow graphs

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Optimizing synchronous systems for multi-dimensional applications 95

Optimizing synchronous systems for multi-dimensional applica...

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European Design and Test (ED&TC) Conference

作者： N.L. Passos E.H.-M. Sha Liang-Fang Chao Department of Computer Science & Engineering University of Notre Dame Notre Dame IN USA Department of Electrical & Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)9780818670398

Time-critical sections of multi-dimensional problems, such as image processing applications, are in general iterative or recursive. In this paper these sections are modeled us cyclic multi-dimensional data flow graphs (MDFGs), which are also used to represent the digital circuit designed to compute such problems. Each node in the MDFG is associated with a set of functional elements in the circuit. Memory elements and circuit paths are associated with graph edges representing data dependencies. This new optimization technique consists of a multi-dimensional re-timing being applied to the MDFG to reduce its cycle time while considering memory requirements. This technique guarantees that all functional elements of a circuit, designed to be applied to problems involving more than one dimension, can be executed simultaneously. The algorithm runs in O.< >

关键词： Delay Application software Design optimization data flow computing Digital circuits Circuit synthesis Registers Concurrent computing Computer science Time factors

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Mapping Control-Intensive Video Kernels onto a Coarse-Grain Reconfigurable Architecture: the H.264/AVC Deblocking Filter

Mapping Control-Intensive Video Kernels onto a Coarse-Grain ...

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Design, Automation and Test in Europe Conference and Exhibition

作者： C. Arbelo A. Kanstein S. Lopez J. F. Lopez M. Berekovic R. Sarmiento J.-Y. Mignolet Research Institute for Applied Microelectronics (IUMA) Department of Electronic Engineering and Control (DIEA) University of Las Palmas Spain Freescale Inc. Toulouse France IMEC vzw Leuven Belgium

ISBN: (纸本)9783981080124

Deblocking filtering represents one of the most compute intensive tasks in an H.264/AVC standard video decoder due to its demanding memory accesses and irregular data flow. For these reasons, an efficient implementation poses big challenges, especially for programmable platforms. In this sense, the mapping of this decoder's functionality onto a C-programmable coarse-grained reconfigurable architecture named ADRES (architecture for dynamically reconfigurable embedded systems) is presented in this paper, including results from the evaluation of different topologies. The results obtained show a considerable reduction in the number of cycles and memory accesses needed to perform the filtering as well as an increase in the degree of instruction parallelism (ILP) when compared with an implementation on a very long instruction word (VLIW) dedicated processor. This demonstrates that high ILP is achievable on the ADRES even for irregular, data-dependent kernels

关键词： Kernel Reconfigurable architectures Automatic voltage control Filtering Decoding VLIW Filters data flow computing Embedded system Topology

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