In this paper efficient VLSI architectures for three modern symmetric block ciphers RC5-32/12/16, SAFER K-128 and 3WAY are discussed. The connection between algorithm properties and VLSI architectures are described. A...
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In this paper efficient VLSI architectures for three modern symmetric block ciphers RC5-32/12/16, SAFER K-128 and 3WAY are discussed. The connection between algorithm properties and VLSI architectures are described. An exemplary performance analysis and comparison of VLSI architectures for a 0.7 /spl mu/m CMOS standard cell process are carried out. The results of the work are reusable soft and firm cores, which can be embedded in integrated systems and allow high speed data encryption. One of the developed VLSI architectures for the 3WAY algorithm achieves a data throughput up to 1.6 Gbit/s, which is up to now the highest encryption speed of a sym. block cipher realized in a CMOS process.
The author proposes the re-documentation of programs with outlines. The interesting feature of outlines is that they allow one to contract, as in a zoom, the amount of information necessary to understand programs, eas...
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The author proposes the re-documentation of programs with outlines. The interesting feature of outlines is that they allow one to contract, as in a zoom, the amount of information necessary to understand programs, easing the localization of given computations or identification of the role of a piece of code. As a first stage toward a framework of program outlines, she has defined a model suited to the representation of computations performed within loops. The main feature of the outlines is that they are both formal and conceptual: they are represented within frames which are semantically equivalent to the outlined loop and help understanding what is computed by revealing how this is computed. In order to re-document loops, she implemented a system, PRISME, able to automatically construct outlines of a subset of Lisp looping functions. PRISME allowed one to validate the implementation of the model. Currently, she uses it intensively to experiment the role of outlines for debugging and reverse specification of programs.
In this paper, we base on datacomputing blocks (DCBs) and DCT watchdog technology to implement VLIW watchdog processor. 32-bit final DCT signature (F-DCT-S) and several 5-bit relay DCT signatures (R-DCT-S) will be co...
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In this paper, we base on datacomputing blocks (DCBs) and DCT watchdog technology to implement VLIW watchdog processor. 32-bit final DCT signature (F-DCT-S) and several 5-bit relay DCT signatures (R-DCT-S) will be computed by DCT watchdog scheme. These generated signatures are embedded into the instruction memory and then used to do the run time error checking. We use VLIW processor to simulation. In this paper, the processor degradation can be improved by doing the whole block error checking after the branch instruction, the fault detection latency is improved by doing the intermediate error checking at the R-type instruction, and the memory overhead is reduced by storing the R-DCT-S to the R-type instruction. The experimental results show that the proposed watchdog has a very high error detection coverage and shortest error detection latency to detect either single fault or multi-faults, no matter what the fault is transient or intermittent.
The Munich Simulation Engine accelerates compiler-driven simulation and is able to exploit a design's parallelism without restrictions. Advocates of table-driven simulation-engines, however, claim that concerning ...
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The Munich Simulation Engine accelerates compiler-driven simulation and is able to exploit a design's parallelism without restrictions. Advocates of table-driven simulation-engines, however, claim that concerning timing simulation the advantage of compiler-driven simulation engines only exists for zero-delay and, maybe, unit-delay simulation. Based on experience with an operational model of the Munich Simulation Computer, it is shown how to define all types of timing models for compilers-driven simulation and to discuss how far the performance potential of the Munich Simulation Computer is affected when timing models are coded and executed by means of event-flow graphs.< >
Summary form only given. The authors report a case study of data-flow software pipelining, an efficient code-mapping strategy for array operations in loops on a highly pipelined static data-flow processor architecture...
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Summary form only given. The authors report a case study of data-flow software pipelining, an efficient code-mapping strategy for array operations in loops on a highly pipelined static data-flow processor architecture based on an argument-fetching data-driven principle. The new architecture has the potential of keeping the instruction-processing pipeline full busy as long as the structure of the program can keep enough enabled instructions for concurrent execution-one main objective of data-flow software pipelining proposed in this work.< >
An automatic method for computing the expected execution time of jobs based on Petri nets is proposed. With this method a job operation flow is modeled using the timed Petri net, all operation cases for every fault ar...
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An automatic method for computing the expected execution time of jobs based on Petri nets is proposed. With this method a job operation flow is modeled using the timed Petri net, all operation cases for every fault are considered using the reachability tree of the Petri net, and the expected execution time is computed automatically. A support system that actualizes the proposed method on a workstation is described. This approach allows job operation flows to be planned without misunderstandings.< >
We have studied tools and techniques to assist integrated modular avionics (IMA) platform design. We propose an approach that helps to decide whether a set of systems can be implemented on an IMA architecture while en...
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We have studied tools and techniques to assist integrated modular avionics (IMA) platform design. We propose an approach that helps to decide whether a set of systems can be implemented on an IMA architecture while enforcing safety requirements. To support the dialogue between teams in charge of defining system architectures and the avionics architecture designers the approach is based on the exchange of allocations constraints. The approach is made of three main steps: system designers describe formally how failures propagate in the system under study and derive segregation constraints, IMA designers collect the constraints and use a constraint solver to generate safe allocations, system designers use this allocation to combine the system failure propagation model with an avionics platform model in order to check quantitative safety requirements. The approach is supported by a set of tools including fault-tree analysers and constraint solvers.
This paper proposes a framework to support the development and use of tools that support the teaching of software and Web engineering. It describes the evolution of tools to support the teaching of software engineerin...
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This paper proposes a framework to support the development and use of tools that support the teaching of software and Web engineering. It describes the evolution of tools to support the teaching of software engineering from simple client-side tools that support drawing DFDs and UML diagrams to Web-based repositories that support process modelling. The paper specifically introduces the concept of "automated walkthroughs" and describes their use within the WWW. It also describes tools that automatically create automated walkthroughs for the World Wide Web (WWW) and their evaluation within a masters-level software engineering module. Conclusions are drawn about the general applicability of the framework and proposals are made for further work in this area.
The visualization of scalar functions of two variables is a classic and ubiquitous application. We present a new method to visualize such data. The method is based on a nonlinear mapping of the function to a height fi...
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ISBN:
(纸本)0780372018
The visualization of scalar functions of two variables is a classic and ubiquitous application. We present a new method to visualize such data. The method is based on a nonlinear mapping of the function to a height field, followed by visualization as a shaded mountain landscape. The method is easy to implement and efficient, and leads to intriguing and insightful images: The visualization is enriched by adding ridges. Three types of applications are discussed: visualization of iso-levels, clusters (multivariate data visualization), and dense contours (flow visualization).
Extraction of complex data structures like vector field topologies in large-scale, unsteady flow field datasets for the interactive exploration in virtual environments cannot be carried out without parallelization str...
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Extraction of complex data structures like vector field topologies in large-scale, unsteady flow field datasets for the interactive exploration in virtual environments cannot be carried out without parallelization strategies. We present an approach based on Nested OpenMP to find critical points, which are the essential parts of velocity field topologies. We evaluate our parallelization scheme on several multi-block datasets, and present the results for various thread counts and loop schedules on all parallelization levels. Our experience suggests that upcoming massively multi-threaded processor architectures can be very advantageously for large-scale feature extractions
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