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检索条件"主题词=Data Flow Computing"

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A special purpose parallel processing ASIC for the first-level calorimeter trigger for the ATLAS detector

A special purpose parallel processing ASIC for the first-lev...

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International Conference on ASIC

作者： M. Engstrom C. Bohm S. Hellman K. Prytz S. Silverstein N. Yamdagni X. Zhao R. Sundblad A. Craciunescu S. Gustafsson A. Odmark P. Bodo Department of Physics University of Stockholm Stockholm Sweden Sicon AB Linkoping Sweden IMC AB Linkoping Sweden

Modern high energy physics experiments require massively parallel special purpose computers (triggers) to reduce the extremely large primary data flow to manageable amounts. We present a prototype processing ASIC intended as the basic computational unit in a first-level calorimeter trigger for the ATLAS collider detector to be built at CERN, Switzerland. The proposed trigger is a compact highly parallel pipelined system with 4096 systolic processors partitioned into 256 weakly-interacting custom-designed ASICs. Local results from these ASICs are then merged by a second, less complex type of ASIC. data is received at 800 Mbit/s by bipolar input circuits, while the processing is performed in CMOS at 320 MHz, using the true single phase clocking scheme (TSPC). This method promotes fast and compact implementations well suited for pipelined bit-serial applications. A 0.5 /spl mu/m BiCMOS process with 4 metal layers was chosen for the implementation.

关键词： Parallel processing Application specific integrated circuits Concurrent computing data flow computing Physics computing Energy management Prototypes Detectors CMOS process Clocks

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Scalable Pattern-Matching via Dynamic Differentiated Distributed Detection (D4)

Scalable Pattern-Matching via Dynamic Differentiated Distrib...

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IEEE GLOBECOM 2008 - 2008 IEEE Global Telecommunications Conference

作者： Kai Zheng Hongbin Lu IBM China Research Laboratory China Department of Computer Science Tsinghua University Beijing China

Pattern Matching (PM) over network packet flows for Network Intrusion Detection/Prevention System is becoming more and more performance sensitive due to the rapid progress of Internet applications in terms of data volumes. Meanwhile, modern multicore platforms are becoming performance competitive with traditional hardware solutions for PM. But due to the unbalance of network flow sizes, traditional flow- based data parallel processing/programming model can not fully exert multicore platforms' computing power and results in poor performance scalability. In this paper, a novel parallel inspection model, Dynamic Differentiated Distributed Detection (D 4 ) is proposed. D 4 deploys distributed parallel operations by adding one more dimension on workload partition/allocation. It proposes an effective and efficient scheme to pre-partition the pattern set in several candidate ways, called "Detection Modes", and let multiple candidate PM methods to handle the subsets, respectively; the most suitable Detection Mode would be selected specifically for each incoming flows at the run-time, and the workload would be dynamically allocated among multiple CPU cores. Experimental results on real-world pattern set and traffic traces show that D 4 scales much better than traditional schemes by better balancing the load among the processors while avoiding unnecessary overheads.

关键词： Multicore processing Pattern matching Intrusion detection IP networks Hardware Parallel processing Parallel programming Computer networks Concurrent computing data flow computing

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Mapping high-dimension wavefront computations to silicon

Mapping high-dimension wavefront computations to silicon

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International Conference on Application Specific Array Processors

作者： C.-M. Wu R.M. Owens M.J. Irwin Department of Computer Science Pennsylvania State University University Park PA USA

The authors present a new template-matching algorithm with good recognition performance. However, this new algorithm exhibits a complex, four-dimensional, wavefront architecture. Thus, for VLSI implementation, reduced architectures with fewer connections and processors need to be derived. For this purpose, the authors develop a systematic reduction methodology to manually map wavefront computations from high-dimension to low-dimension. This methodology consists of seven steps. Based on this methodology, the authors derive several two-dimensional architectures which are suitable for VLSI implementation for the new template-matching algorithm and have simulated one of the architectures by using the Intel Hypercube Machine iPSC/2.< >

关键词： Silicon Very large scale integration Computer architecture data flow computing Computational modeling Heuristic algorithms Computer science flow graphs Shift registers Hypercubes

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A flow analysis technique for parallel computations

A flow analysis technique for parallel computations

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International Phoenix Conference on Computers and Communications (IPCCC)

作者： R. Ammar B. Qin U-155 Computer Science & Engineering Department University of Connecticut Storrs CT USA

A flow-analysis technique for real-time parallel computations at the computation level is presented. The technique is based on reducing the given parallel computation to a sequential one and then applying one of the a... 详细信息

关键词： Concurrent computing flow graphs Computational modeling Performance analysis Costs Software performance Intelligent robots data flow computing Computer science Parallel processing

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JPG - a partial bitstream generation tool to support partial reconfiguration in virtex FPGAs

JPG - a partial bitstream generation tool to support partial...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： A.K. Raghavan P. Sutton Motorola Australia Software Centre Adelaide SA Australia School of Information Technology and Electrical Engineering University of Queensland Brisbane QLD Australia

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Speech recognition HMM training on reconfigurable parallel processor

Speech recognition HMM training on reconfigurable parallel p...

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Annual IEEE Symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Hyun-Kyu Yun A. Smith H. Silverman Division of Engineering BOX D Brown University Providence RI USA

Armstrong III is a 20 node multi-computer that is currently operational. In addition to a RISC processor, each node contains reconfigurable resources implemented with FPGAs. The in-circuit reprogramability of static RAM based FPGAs allows the computational capabilities of a node to be dynamically matched to the computational requirements of an application. Most reconfigurable computers in existence today rely solely on a large number of FPGAs to perform computations. In contrast, the paper demonstrates the utility of a small number of FPGAs coupled to a RISC processor with a simple interconnect. The article describes a substantive example application that performs HMM training for speech recognition with the reconfigurable platform.

关键词： Speech recognition Hidden Markov models Field programmable gate arrays data flow computing Pipeline processing flow graphs Reduced instruction set computing Computer architecture Signal processing algorithms Parallel processing

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On the Difficulties of Using Workflow Tools to Express Parallelism and Distribution– An Application Case Study in Geological Sciences

On the Difficulties of Using Workflow Tools to Express Paral...

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International Conference on Grid and Pervasive computing Workshops, GPC

作者： Luis Assunção Carlos Gonçalves José C. Cunha Instituto Superior de Engenharia de Lisboa Portugal CITI/Dept. Informática Universidade Nova de Lisboa Portugal

We discuss the parallelization and distribution of a workflow based application. We present experimental results and discuss lessons learned. The experimentation is based on a scientific application case study - sequential simulation applied to geostatistics. As a result we identify a list of issues not well supported in the most referenced scientific workflows tools and environments namely Kepler, and outline relevant research directions.

关键词： Geology Problem-solving Parallel processing Large-scale systems Partitioning algorithms Scalability Yarn Pervasive computing data flow computing Geoscience

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It Does Matter How You Normalise the Branch Distance in Search Based Software Testing

It Does Matter How You Normalise the Branch Distance in Sear...

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International Conference on Software Testing, Verification, and Validation, ICST

作者： Andrea Arcuri Simula Research Laboratory Lysaker Norway

The use of search algorithms for test data generation has seen many successful results. For structural criteria such as branch coverage, heuristics have been designed to help the search. The most common heuristic is the use of approach level (usually represented with an integer) to reward test cases whose executions get close (in the control flow graph)to the target branch. To solve the constraints of the predicates in the control flow graph, the branch distance is commonly employed. These two measures are linearly combined. Because the approach level is more important, the branch distance is normalised, often in the range. In this paper, we analyse different types of normalising functions. We found out that the one that is usually employed in the literature has several flaws. We hence propose a different normalizing function that is very simple and that does not suffer of these limitations. We carried out empirical and analytical analyses to compare these two functions. In particular, we studied their effect on two commonly used search algorithms, namely Simulated Annealing and Genetic Algorithms.

关键词： Software testing Software algorithms flow graphs Simulated annealing Genetic algorithms Software engineering Application software Laboratories data flow computing Automatic control

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A dynamically reconfigurable interconnection chip

A dynamically reconfigurable interconnection chip

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IEEE International Conference on Solid-State Circuits (ISSCC)

作者： Chin-Yuan Chin Wen-Tai Lin Juh-Ping Hwang Sow Chu G. Forman R. Dunki-Jacobs S. Karr J. Mallick H. Kung A. Sussman F.H. Hsu T. Nishizawa General Electric Corporate Research and Development Center Schenectady NY USA Union College Schenectady NY USA Department of Computer Science Carnegie Mellon University Pittsburgh PA USA

This paper will describe a 70K transistor chip fabricated in a 1.25μm CMOS technology, with a 6.2×7.6mm die size, and featuring data synchronization, pipeline latency compensation and other computational elements.

关键词： Delay Pipeline processing Computer interfaces data flow computing Processor scheduling Synchronization Clocks Shift registers Research and development Systolic arrays

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Extension of Winograd multiplicative algorithm to transform size N=p/sup 2/q and its implementation

Extension of Winograd multiplicative algorithm to transform ...

引用

International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： C. Lu R. Tolimieri Electrical Engineering Department/CCNY CUNY New York NY USA

The authors continue a program of designing multiplicative FFT (fast Fourier transform) algorithms with highly structured data flow. They take up the case of transform size N, N=p/sup 2/q, where p and q are distinct odd primes. Number-theoretical methods are used to decompose the indexing set into orbits based on its multiplicative ring structure of Z/N, N=p/sup 2/q. A family of variants of the fundamental algorithm is designed, presenting options as to whether additions or multiplications dominate arithmetic cost.< >

关键词： Indexing Algorithm design and analysis Arithmetic Costs Cathode ray tubes Chaos Large-scale systems data flow computing Orbits Fourier transforms

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