Functional-structural Plant Models are interesting tools to study interactions between architecture and environmental conditions. In the case of Winter Oilseed Rape (WOSR), we need a plant model that accounts for the ...
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ISBN:
(纸本)9781424463299
Functional-structural Plant Models are interesting tools to study interactions between architecture and environmental conditions. In the case of Winter Oilseed Rape (WOSR), we need a plant model that accounts for the role of source:sink relationships in the architectural development. GreenLab model is a good candidate because it was already used to evidence interactions between source:sink relationships and architecture for other species. However, its adaptation to WOSR is a challenge because of the complexity of its developmental scheme especially during reproductive phase. Indeed, we need to take into account the different timings of branch expansion and pod setting. Therefore two equations were added in GreenLab model to compute expansion delays for respectively branching and flowering of each *** field data were used to estimate morphological parameters such as phyllochron, podochron,(equivalent to phyllochron but for pods), leaf expansion duration, and leaf life span. These data were also used to calibrate the source:sink module of the model. First results indicated that the model simulates properly the dynamics of plant growth and development during both vegetative and reproductive phases.
Shallow, narrow and busy channels do not easily allow conventional current measurements in real time. The goal is to investigate the possibility of using data of a horizontally mounted ADCP for measuring flow velocity...
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Shallow, narrow and busy channels do not easily allow conventional current measurements in real time. The goal is to investigate the possibility of using data of a horizontally mounted ADCP for measuring flow velocity and direction in a river or channel. Measurements were performed during one month with a horizontally mounted ADCP in a 400 m wide waterway in the Port of Rotterdam. Two horizontal acoustic beams point from one shore to the other. The authors compare the horizontal ADCP data with the data of a vessel-mounted ADCP. It has been shown that the horizontal ADCP averages flow over a certain part of the water column. The authors propose a method to compute river flow averaged over the total cross section from horizontal ADCP data. The horizontal ADCP results compare well with vessel mounted ADCP data for two tidal cycles.
Real-time cyclic spectral analysis is useful in many applications, but is difficult to achieve because of its computational complexity. This paper studies the distribution of complex multipliers in multiprocessor cycl...
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Real-time cyclic spectral analysis is useful in many applications, but is difficult to achieve because of its computational complexity. This paper studies the distribution of complex multipliers in multiprocessor cyclic spectrum analyzers, with the objective of obtaining computational balance. Computationally balanced implementations efficiently use hardware so that computational bottlenecks are reduced and a smooth flow of data between computational sections of the analyzer is maintained. Tables are presented that give the number of complex multipliers required in each section of the analyzer to obtain computational balance.< >
The authors report on a model of error detection called RELAY, which provides a fault-based criterion for test data selection. The RELAY model builds on the testing theory introduced by M.H. Morell (1981), where an er...
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The authors report on a model of error detection called RELAY, which provides a fault-based criterion for test data selection. The RELAY model builds on the testing theory introduced by M.H. Morell (1981), where an error is created when an incorrect state is introduced at some fault location and is propagated if it persists to the output. The authors refine this theory by more precisely defining the notion of when an error is introduced and by differentiating between the persistence of an error through computations and its persistence through data-flow operations. They introduce similar concepts, origination and transfer, as the first erroneous evaluation and the persistence of that erroneous evaluation respectively.< >
We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these s...
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We describe a high-level design method to synthesize multi-phase regular arrays. The method is based on deriving component designs using classical regular (or systolic) array synthesis techniques and composing these separately evolved component designs into a unified global design. Similarity transformations are applied to component designs in the composition stage in order to align dataflow between the phases of the computations. Three transformations are considered: rotation, reflection and translation. The technique is aimed at the design of hardware components for high-throughput embedded systems applications and we demonstrate this by deriving a multi-phase regular array for the 2D DCT algorithm which is widely used in many video communications applications.
General purpose computation based on GPU is a hot topic for research in recent years. The paper presents the parallel implementation of Viterbi algorithm on GPU based on features of GPU and characteristics of Viterbi ...
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ISBN:
(纸本)9781424449095
General purpose computation based on GPU is a hot topic for research in recent years. The paper presents the parallel implementation of Viterbi algorithm on GPU based on features of GPU and characteristics of Viterbi algorithm in keyword spotting system. The results of examination by using NVIDIA 9600 GT GPU show that the GPU, in comparison to traditional processing platform, could enhance the processing performance if the recognition accuracy of keyword spotting system is ensured.
Scheduling meta applications on a computational grid uses estimation of the execution times of component programs to compute optimal schedules. In a realistic case various factors (hazards) lead to estimation errors, ...
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Scheduling meta applications on a computational grid uses estimation of the execution times of component programs to compute optimal schedules. In a realistic case various factors (hazards) lead to estimation errors, which affect both the performance of a schedule and resource utilization. We introduce the concept of robustness and present an analysis technique to determine the robustness of a schedule. We develop methods for reducing the chance that a metaprogram exceeds its execution time due to components outside its critical path. The results of this analysis are used to compute schedules less sensitive to hazards. This translates into more accurate reservation requirements for critical systems, and reduced expected execution time for non-critical metaprograms executed repeatedly. Simulation results prove the efficiency and applicability of our algorithms.
In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimiz...
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In this paper, we present a low power targeted high-level synthesis framework for the synthesis of single chip Application Specific DSP (Digital Signal Processing) architectures. This new framework is based on minimizing the switching activity on the functional units as well as the global buses. The main focus of the developed method is minimizing the power during partitioning and binding phases of high-level synthesis. A Stochastic Evolution based technique has been used for partitioning the given dataflow graph describing the DSP algorithm. Experimental results were highly encouraging with power reduction of up to 60% on certain benchmark designs.
A novel algorithm for parallel design verification is described. Its data model is that of the dataflow computer and is based on the partitioning of the design verification cycle into independent tasks that can be ru...
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A novel algorithm for parallel design verification is described. Its data model is that of the dataflow computer and is based on the partitioning of the design verification cycle into independent tasks that can be run concurrently. The significance of this methodology is that, unlike other concepts that cannot use the existing sequential code and can only run on an expensive special-purpose hardware, the proposed approach does not require any code development and can be accommodated by a standard Unix distributed network or a multiprocessor. The author presents experimental results for performing 52 design rule checks on 1.3 million polygons (12 layers) on both a multiprocessor configuration and a distributed network.< >
The authors propose a distributed military premises network architecture (DIPNET) for a wide range of campuslike military premises integrated services digital network (ISDN) applications. DIPNET is to offer integrated...
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The authors propose a distributed military premises network architecture (DIPNET) for a wide range of campuslike military premises integrated services digital network (ISDN) applications. DIPNET is to offer integrated voice, data, and video services to the end-users for both premises network and network interface applications, and it has taken the network security, survivability, reconfigurability, and ISDN interface requirements into the design considerations. DIPNET conforms with the military communications goals of standardized interfaces and intelligent premises networks.< >
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