检索结果-内蒙古大学图书馆

Dynamical Self-Reconfigurable Mechanism for data-Driven Cell Array

Journal of Shanghai Jiaotong university(Science) 2021年第4期26卷 511-521页

作者： SHAN Rui JIANG Lin WU Haoyue HE Feilong LIU Xinchuang School of Electronic Engineering Xi’an University of Posts and TelecommunicationsXi’an710121China Laboratory of Integrated Circuit Design Xi’an University of Science and TechnologyXi’an710054China School of Computing Xi’an University of Posts and TelecommunicationsXi’an710121China

The utilization of computation resources and reconfiguration time has a large impact on reconfiguration system performance. In order to promote the performance, a dynamical self-reconfigurable mechanism for data-driven cell array is proposed. Cells can be fired only when the needed data arrives, and cell array can be worked on two modes: fixed execution and reconfiguration. On reconfiguration mode, cell function and data flow direction are changed automatically at run time according to contexts. Simultaneously using an H-tree interconnection network, through pre-storing multiple application mapping contexts in reconfiguration buffer, multiple applications can execute concurrently and context switching time is the minimal. For verifying system performance, some algorithms are selected for mapping onto the proposed structure, and the amount of configuration contexts and execution time are recorded for statistical analysis. The results show that the proposed self-reconfigurable mechanism can reduce the number of contexts efficiently, and has a low computing time.

关键词： cell array configurable computing self-reconfigurable mechanism data-driven data flow graph

来源：评论

学校读者我要写书评

暂无评论

GNN4IP: graph Neural Network for Hardware Intellectual Property Piracy Detection 58

GNN4IP: Graph Neural Network for Hardware Intellectual Prope...

引用

58th ACM/IEEE Design Automation Conference (DAC)

作者： Yasaei, Rozhin Shih-Yuan Yu Naeini, Emad Kasaeyan Al Faruque, Mohammad Abdullah Univ Calif Irvine Dept Elect Engn & Comp Sci Irvine CA 92697 USA

ISBN: (纸本)9781665432740

Aggressive time-to-market constraints and enormous hardware design and fabrication costs have pushed the semiconductor industry toward hardware Intellectual Properties (IP) core design. However, the globalization of the integrated circuits (IC) supply chain exposes IP providers to theft and illegal redistribution of IPs. Watermarking and fingerprinting are proposed to detect IP piracy. Nevertheless, they come with additional hardware overhead and cannot guarantee IP security as advanced attacks are reported to remove the watermark, forge, or bypass it. In this work, we propose a novel methodology, GNN4IP, to assess similarities between circuits and detect IP piracy. We model the hardware design as a graph and construct a graph neural network model to learn its behavior using the comprehensive dataset of register transfer level codes and gate-level netlists that we have gathered. GNN4IP detects IP piracy with 96% accuracy in our dataset and recognizes the original IP in its obfuscated version with 100% accuracy.

关键词： Hardware intellectual property- IP piracy graph convolutional network data flow graph

来源：评论

学校读者我要写书评

暂无评论

Fusion of powerful features of Harris Hawks with Cuckoo Search algorithm for engineering applications

引用

RESULTS IN CONTROL AND OPTIMIZATION 2023年 13卷

作者： Kaur, Mandeep Kaur, Ranjit Singh, Narinder Punjabi Univ Dept Elect & Commun Engn Patiala Punjab India Punjabi Univ Dept Math Patiala Punjab India

The High-level synthesis (HLS) is a key step in the digital VLSI circuit design. HLS can be seen in the present study as an important matter of intelligently map a data flow graph (DFG) specification of digital filters to FPGA. In this article, the powerful features of the Harris hawks optimization (HHO) and Cuckoo search (CS) algorithm have improved the performance of the proposed method. This proposed strategy is also known as the GChO algorithm. In GChO, the phase of CS helps to force the HHO to escape from stagnation, to ignore local optima and premature convergence. In addition for HLS, the three retiming-based models were also proposed in the work. The standard pipelining was employed in Model 1. The modified MinPeriod Retiming on the multiplier less digital filters was incorporated by Model 2 and led to a significant improvement in clock frequency. Model 3 adopted modified Min -Area Retiming on digital filters and reduced the complexity of the circuit;however these designs therefore offer single parameter -based heuristic solution. This can be resolved by using meta -heuristic approach focused on retiming. The use of meta -heuristic methods and swarm intelligence has been considered as a highly desirable choice when searching the digital block solution space with higher frequency and reduced complexity in HLS problems. The robustness of the GChO method has been verified on IEEE CEC' 2020 standard benchmark test suites. The paper analyzes that the performance of the proposed GChO algorithm outperforms the Harris hawks optimization (HHO), Moth Flame optimization algorithm, Particle Swarm optimization algorithm, Chimp optimization algorithm for the HLS digital filters. The experimental results show that the proposed Model 2 and 3 for retimed PDR-FIR filter is improved in term of MUF by 7.38% and utilized slices by 37.77%, PRO-DFII IIR retimed filter by 10.54%, and complexity reduced by 29.69%, PRO-LAT-ARF by 41.61% and slice by 11.17% and PRO-LATLAD-IIR improved

关键词： High Level Synthesis (HLS) data flow graph Johnson algorithm Min-Period Retiming Min-Area Retiming Field Programmable Gate Array (FPGA) Evolutionary algorithms

来源：评论

学校读者我要写书评

暂无评论

Optimal Resource Allocation and Binding in High-Level Synthesis Using Nature-Inspired Computation 3rd

Optimal Resource Allocation and Binding in High-Level Synthe...

引用

3rd International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT)

作者： Shilpa, K. C. LakshmiNarayana, C. Singh, Manoj Kumar Dr Ambedkar Inst Technol Bangalore Karnataka India BMSCE Dept Elect Engn Sci Bangalore Karnataka India Manuro Tech Res Bangalore Karnataka India

ISBN: (纸本)9789811358029;9789811358012

Allocation of resource and binding it to functional unit at high-level synthesis an optimal problem to minimize the area and performance in terms of resource sharing and binding is presented in this paper. The paper presents the comparative analysis of nature-inspired computation techniques for resource allocation and binding: 1. Evolutionary-based computation: genetic algorithm. 2. Swarm intelligence-based computation: particle swarm optimization. The comparative analysis of the results shows genetic algorithm surpasses particle swarm optimization in providing the precise mapping between the operation and functional unit sharing with zero errors in resource allocation.

关键词： data flow graph Genetic algorithm High-level synthesis Integer linear programming Particle swarm optimization Register-transfer level

来源：评论

学校读者我要写书评

暂无评论

A Software Framework for Adaptive Signal Analytics based on Autonomic Service Components 19

A Software Framework for Adaptive Signal Analytics based on ...

引用

12th Innovations in Software Engineering Conference (ISEC)

作者： Mohapatra, Pragyan Sinha, Rahul IIIT Bangalore Karnataka India TCS Res Bangalore Karnataka India

ISBN: (纸本)9781450362153

The design of platforms for analyzing signals/data requires encoding domain knowledge, defining programming language abstractions and creating an adaptive runtime environment which interfaces with the environment, to enable meaningful inferences. The platform needs to be data driven and context aware. An appropriate computational tool in the platform should enable an automated selection of algorithms and data for making the right inferences with a specified performance. Towards designing a software platform for analyzing data, deriving data driven models, selection of algorithms and enabling feedback mechanisms for adaptation, we propose a service oriented software architecture based on autonomic service components. This approach enables goal relevant decision making and data driven adaptation. The use of Service Component Ensemble Language (SCEL) is highlighted for signal pre-processing based on data driven models. A service broker architecture is proposed to aid in composing services to enable enable algorithm selection and execution for signal pre-processing on biomedical signals for clinical inferences

关键词： data flow graph Signal processing Autonomic service components Quality based service composition data driven models

来源：评论

学校读者我要写书评

暂无评论

Energy Efficient Runtime Approximate Computing on data flow graphs 17

Energy Efficient Runtime Approximate Computing on Data Flow ...

引用

IEEE/ACM 36th International Conference on Computer-Aided Design (ICCAD)

作者： Gao, Mingze Qu, Gang Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Univ Maryland Inst Syst Res College Pk MD 20742 USA

ISBN: (纸本)9781538630938

Approximate computing is an emerging computation paradigm that utilizes many applications' intrinsic error resilience to improve power and energy efficiency. Several approaches have been proposed to identify the non-critical computations by analyzing the output sensitivity to the accuracy of the results, and then perform approximate computing on these computations. However, these static approaches only use the prior knowledge (e.g. input ranges) for analysis and fail to consider the runtime information, which limits the energy saving and incurs large computation error. In this paper, we propose a runtime approximate computing framework to solve this problem. The basic idea is to use a low cost method to estimate the impact of each immediate input value to the accuracy of computation at every node in the data flow graph, and then decide whether we should simply use the estimated value or perform an accurate computation. Our novel runtime estimation method is based on converting data to the logarithmic representation. We propose two algorithms to make the decision at certain nodes whether an accurate computation will be needed to balance energy saving and computation error. Experimental results show that this tradeoff ranges from 40% energy saving with 4.85% error on average to 8% energy saving with 0.18% error. Compared to the static DFG node cutting approach, our approach's estimation accuracy is 32x better to achieve the same amount of energy saving.

关键词： Energy efficient data flow graph approximate computing logarithmic estimation runtime

来源：评论

学校读者我要写书评

暂无评论

A System for Exploratory Analysis in Cloud 5

A System for Exploratory Analysis in Cloud

引用

5th IEEE International Conference on Cyber Security and Cloud Computing (CSCloud) / 4th IEEE International Conference on Edge Computing and Scalable Cloud (EdgeCom)

作者： Guo, Liangchen Zhang, Yazhong Lu, Chang Jing, Yinan He, Zhenying Wang, X. Sean Fudan Univ Data Anal & Secur Lab Shanghai Peoples R China

ISBN: (纸本)9781538658505

This paper designs and implements a system which provides interactive data analysis services in cloud. These services allow users to analyze and explore large-scale in-cloud datasets quickly and interactively with a simple graphical user interface by leveraging the distributed computing ability of cloud data computing engine. The system decouples the analysis process and the computing engine. Users can construct the data flow graph in GUI, and review the results that are presented through the visualization tools. The back-end of the system is responsible for converting data flow graphs to the computation jobs that can be executed in cloud clusters. In addition, the system makes full use of the characteristics of overlapping results in the interactive analysis, and avoids repetitive computation through the caching mechanism. As a consequence, with this system, we make it easy and fast to perform interactive exploratory data analysis in cloud without losing flexibility.

关键词： exploratory analysis data flow graph cloud computing

来源：评论

学校读者我要写书评

暂无评论

High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures 8

High Level Synthesis for Retiming Stochastic VLSI Signal Pro...

引用

8th International Conference on Advances in Computing & Communications (ICACC)

作者： Krishnapriya, P. N. Sundari, B. Bala Tripura Amrita Vishwa Vidyapeetham Amrita Sch Engn Dept Elect & Commun Engn Coimbatore Tamil Nadu India

With high integration density due to scaling of IC fabrication processes, faster design cycles, are the need of today along with development of energy efficient architectures fulfilling the speed requirements. The focus here is the to build up features of stochastic computing for data centric or data steaming applications. High level synthesis (HLS) allows the designer to incorporate transformations on the applications before the register transfer level (RTL) generation to incorporate design space explorations. Herein the design space explorations start with retiming. Also the novelty is that filter bench marks considered are implemented by incorporating stochastic computing functions. The same are used to develop the filter benchmarks and then retiming transformation is applied in HLS. The design space trade off results with respect to retiming transformations on conventional computation and stochastic computing architectures are presented, for area and power and it is found that stochastic computing results in area saving and power saving scales relatively for higher order applications namely the filter benchmarks showing that stochastic structures to be energy efficient than conventional computing. The future scope of the work is to consider accuracy analysis based on end user demand of accuracy versus energy efficiency. (C) 2018 The Authors. Published by Elsevier B.V.

关键词： Stochastic Computing High Level Synthesis data flow graph Retiming Pipelining Design Space Exploration

来源：评论

学校读者我要写书评

暂无评论

DFG partitioning algorithms for coarse grained reconfigurable array assisted RTL simulation accelerators

DFG partitioning algorithms for coarse grained reconfigurabl...

引用

IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)

作者： Mahapatra, Ipsita Biswas Agarwal, Utkarsh Nandy, S. K. Indian Inst Sci CAD Lab Bangalore 560012 Karnataka India Adobe Syst Bangalore 560012 Karnataka India

ISBN: (纸本)9781538611128

As the complexity of circuit design increases, verification of these circuits through simulation also becomes extremely challenging. This creates a bottleneck in the IC design process. Distributed simulation is one way of solving this problem where the simulation workload is distributed among the parallel processors involved in the simulation. However the design has to be carefully partitioned for this purpose. In order to perform distributed simulation, many efficient partitioning algorithms have been proposed till date. These algorithms mostly partition gate level netlist or logic circuits and reduces inter-processor communication by minimizing cutsize for a given constraint of load balance. In this paper, we present two different partitioning schemes for performing distributed simulation. They are: a Discrete Particle Swarm Optimization (DPSO) based partitioning algorithm (DPSO-PA) and an effective partitioning heuristic. These algorithms partitions data flow graph (DFG) for a recently proposed Coarse Grained Reconfigurable Array assisted Hardware Accelerator (CGRA-HA). We also propose an improved version of the original DPSO methodology through careful selection of initial partition sets. It is found that the proposed heuristic based partitioning algorithm outperforms the modified DPSO-PA in terms of lesser cut-edges.

关键词： CGRA Hardware accelerator RTL simulation Distributed simulation data flow graph

来源：评论

学校读者我要写书评

暂无评论

Improving the Expressiveness of Deep Learning Frameworks with Recursion 18

Improving the Expressiveness of Deep Learning Frameworks wit...

引用

13th EuroSys Conference (EuroSys)

作者： Jeong, Eunji Jeong, Joo Seong Kim, Soojeong Yu, Gyeong-In Chun, Byung-Gon Seoul Natl Univ Seoul South Korea

ISBN: (纸本)9781450355841

Recursive neural networks have widely been used by researchers to handle applications with recursively or hierarchically structured data. However, embedded control flow deep learning frameworks such as Tensorflow, Theano, Caffe2, and MXNet fail to efficiently represent and execute such neural networks, due to lack of support for recursion. In this paper, we add recursion to the programming model of existing frameworks by complementing their design with recursive execution of dataflow graphs as well as additional APIs for recursive definitions. Unlike iterative implementations, which can only understand the topological index of each node in recursive data structures, our recursive implementation is able to exploit the recursive relationships between nodes for efficient execution based on parallel computation. We present an implementation on Tensorflow and evaluation results with various recursive neural network models, showing that our recursive implementation not only conveys the recursive nature of recursive neural networks better than other implementations, but also uses given resources more effectively to reduce training and inference time.

关键词： recursive neural network programmability data flow graph deep learning framework automatic differentiation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：