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Multiple-Core PLC CPU Implementation and Programming

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS 2018年第10期27卷

作者： Milik, Adam Silesian Tech Univ Inst Elect Akademicka 16 PL-44100 Gliwice Poland

The paper presents a complete approach to the multithreaded execution of a control program prepared according to IEC61131-3 standard. The program is mapped to a dedicated multiple-core CPU unit. The CPU consists of multiple independent bit and word CPUs. The computation synchronization mechanism is based on memory cells with semaphored access, which enable hardware-level synchronization. The paper presents in detail the architecture, results of implementation and the achieved performance. The custom-developed compiler translates standard programming languages into a multithreaded executable form. It utilizes an original intermediate data flow graph to optimize and recognize program parallelisms. The program is automatically partitioned and mapped to the available computing resources. The paper is concluded with a performance comparison of program executions using the standard single-threaded and proposed approaches.

关键词： PLC LD IL SFC FPGA compiler control program optimization programming data flow graph parallel computation multiple-core CPU

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High Level Synthesis for Retiming Stochastic VLSI Signal Processing Architectures

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Procedia Computer Science 2018年 143卷 10-19页

作者： Krishnapriya P N B. Bala Tripura Sundari

With high integration density due to scaling of IC fabrication processes, faster design cycles, are the need of today along with development of energy efficient architectures fulfilling the speed requirements. The focus here is the to build up features of stochastic computing for data centric or data steaming applications. High level synthesis (HLS) allows the designer to incorporate transformations on the applications before the register transfer level (RTL) generation to incorporate design space explorations. Herein the design space explorations start with retiming. Also the novelty is that filter bench marks considered are implemented by incorporating stochastic computing functions. The same are used to develop the filter benchmarks and then retiming transformation is applied in HLS. The design space trade off results with respect to retiming transformations on conventional computation and stochastic computing architectures are presented, for area and power and it is found that stochastic computing results in area saving and power saving scales relatively for higher order applications namely the filter benchmarks showing that stochastic structures to be energy efficient than conventional computing. The future scope of the work is to consider accuracy analysis based on end user demand of accuracy versus energy efficiency.

关键词： Stochastic Computing High Level Synthesis data flow graph Retiming Pipelining Design Space Exploration

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Temporal partitioning of data flow graph for dynamically reconfigurable architecture

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JOURNAL OF SYSTEMS ARCHITECTURE 2011年第8期57卷 790-798页

作者： Ouni, Bouraoui Ayadi, Ramzi Mtibaa, Abdellatif Fac Sci Lab Elect & Microelect Monastir 5000 Tunisia

In this paper, we present a novel temporal partitioning algorithm that temporally partitions a data flow graph on reconfigurable system. Our algorithm can be used to resolve the temporal partitioning problem at the behaviour level. Our algorithm optimizes the whole latency of the design;this aim can be reached by minimizing the latency of the graph and the number of partitions at the same time. Consequently, our algorithm starts by the lowest possible number of partitions;and next it uses the eigenvectors of the graph to find the best schedule of nodes that minimizes the latency of the graph. The proposed methodology was tested on several examples on reconfigurable architecture based on Xilinx Vertex-II XC2V1000 FPGA device. The results show significant reduction in the design latency compared to famous related algorithms used in this field. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Temporal partitioning Reconfigurable architecture FPGA-engineering VLSI applications Algorithm data flow graph

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DTP: Enabling Exhaustive Exploration of FPGA Temporal Partitions for Streaming HPC Applications 2017

DTP: Enabling Exhaustive Exploration of FPGA Temporal Partit...

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8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART)

作者： Koraei, Mostafa Jahre, Magnus Fatemi, S. Omid Univ Tehran Tehran Iran NTNU Trondheim Norway

ISBN: (纸本)9781450353168

Reconfigurable computing systems show great promise for accelerating streaming HPC applications because of their low power consumption and high performance. However, mapping an HPC application to a reconfigurable system is a challenging task. The challenge is exacerbated by need to temporally partition computational kernels when application requirements exceed resource availability. In this paper, we propose a novel design methodology that we call data-flow Temporal Partitioning (DTP). The key insight in the design of DTP was that the application should be represented as a high-level data flow graph where each node is a computational kernel and the edges represent inter-node data flow. DTP also supports parallel instantiation of kernels and multiple kernel implementations at different performance/area design points. In contrast to previous proposals, DTP is able to exhaustively explore the solution space for practical applications. Our evaluation of DTP shows that it is able to identify candidate implementations that outperform both previously proposed partitioning heuristics and a direct mapping to the synthesis tool. The temporal configuration selected by DTP can outperform the direct mapping by up to 3X.

关键词： High performance computing Field programmable gate array data flow graph Temporal partitioning Design space exploration

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A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delays 4

A comparison of two metaheuristic algorithms for scheduling ...

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4th International Conference on Control, Decision and Information Technologies (CoDIT)

作者： Abdallah, Fadel Tanougast, Camel Kacem, Imed Diou, Camille Singer, Daniel Univ Lorraine LCOMS EA 7306 7 Rue Marconi F-57070 Metz France

ISBN: (纸本)9781509064656

This paper considers the problem of scheduling on a heterogeneous CPU/FPGA architecture with communication delays, with the aim of minimizing the makespan (or the schedule length). For this strongly NP-hard problem, we present two iterative algorithms based on simulated annealing (SA) and genetic algorithms (GAs), which are used to run in the MPSoC an application described in a data flow graph. The performance of the proposed algorithms are evaluated and compared on a set of instances with up to 50 tasks. Computational experiments indicate that the innovative proposed algorithms provide competitive results for the studied problem and that the objective function values obtained are optimal or very close to a lower bound in a reasonable computation time.

关键词： heterogeneous system CPU/FPGA metaheuristics data flow graph makespan (schedule length) genetic algorithm simulated annealing real time task scheduling optimization

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A Novel Model of Computation for Software Synthesis Based on data Frame Driving

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IETE TECHNICAL REVIEW 2015年第1期32卷 70-78页

作者： Wang, Jian Li, Yubai Univ Elect Sci & Technol China Sch Commun & Informat Engn Chengdu 610054 Peoples R China

Software synthesis is a useful technology to accelerate the design of digital systems, and the MoC (model of computation) is the foundation of software synthesis. Current researches on MoC mainly focus on the situations that the produced data frames are used only once by its downstream module. However, for some applications with loops, the data frame produced by upstream module needs to be reused and thus the current MoCs cannot be directly used to synthesize these applications' DFG (data flow graph). To solve this problem, a novel MoC based on data frame driving is proposed for software synthesis in this paper. In our MoC, the DFG with loops is first transformed into an acyclic DFG and modules in the acyclic DFG are divided into different levels that define the priority of modules. Then, the schedule can be generated according to the modules' level. The proposed MoC is verified under both random generated DFG and real-world application's DFG. The experimental results show that by using the proposed MoC, the schedule for DFG with reused data frame can be generated for both single processor system and multi-processors system, and it thus can be used as a useful tool to aid the software synthesis.

关键词： Software synthesis Model of computation data flow graph Scheduling

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Natural Computation for Optimal Scheduling with ILP Modeling in High Level Synthesis

Natural Computation for Optimal Scheduling with ILP Modeling...

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International Conference on Information and Communication Technologies (ICICT)

作者： Shilpa, K. C. LakshmiNarayana, C. Visvesvaraya Technol Univ Dept Elect Engn Sci BMSCE Bangalore 560019 Karnataka India

The concept of the natural computation for optimal scheduling in high level synthesis, for resource constraint and time constraint scheduling problem in automated integrated circuit synthesis using Integer Linear Programming (ILP) modeling is presented in this paper. This paper compares three natural computations paradigms: (i) evolution optimizer technique genetic algorithm, (ii) evolutionary programming, and (iii) swarm intelligence based particle swarm optimization. Experimental results indicate that evolution based Genetic Algorithm search is more powerful search compared to Evolutionary Programming and Particle Swam Optimization. (C) 2015 The Authors. Published by Elsevier B.V.

关键词： High Level Synthesis data flow graph Evolutionary Programming Genetic Algorithm Particle Swarm Optimization Very Large Scale Integration Integer Linear Programming

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Towards Optimal FPGA Implementation of Lattice-Ladder Neuron and Its Training Circuit 3

Towards Optimal FPGA Implementation of Lattice-Ladder Neuron...

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3rd IEEE Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE)

作者： Sledevic, Tomyslav Navakauskas, Dalius Vilnius Gediminas Tech Univ Dept Elect Syst Naugarduko Str 41-413 LT-03227 Vilnius Lithuania

ISBN: (纸本)9781509012015

The FPGA implementation of lattice-ladder multilayer perceptron with its training algorithm seems attractive, however there is a lack of experimental results on its efficiency. The main aim of this investigation was to optimize the latency and DSP block usage for the normalized lattice-ladder neuron (LLN) and its simple gradient training algorithm implementation on FPGA. Four alternative regressor lattices to be used in LLN training were considered and experimentally evaluated. The optimal resource sharing was approached by the LLN data flow graph partitioning into DSP block subgraphs. The experiments were performed by varying the number of synapses and the order of lattice-ladder filters. Recommendations for particular LLN implementation cases were given.

关键词： lattice-ladder neuron data flow graph FPGA implementation high level synthesis fixed-point arithmetic

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Natural Computation for Optimal Scheduling with ILP Modeling in High Level Synthesis

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Procedia Computer Science 2015年 46卷 167-175页

作者： K.C. Shilpa C. LakshmiNarayana BMSCE Department of Electrical Engineering Science Visvesvaraya Technological University Bangalore 560019 India

关键词： High Level Synthesis data flow graph Evolutionary Programming Genetic Algorithm Particle Swarm Optimization Very Large Scale Integration Integer Linear Programming

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Towards Optimal FPGA Implementation of Lattice-Ladder Neuron and Its Training Circuit

Towards Optimal FPGA Implementation of Lattice-Ladder Neuron...

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IEEE Workshop on Advances in Information, Electronic and Electrical Engineering

作者： Tomyslav Sledevi? Dalius Navakauskas Department of Electronic Systems Vilnius Gediminas Technical University Naugarduko str. 41-413 LT-03227 Vilnius Lithuania

ISBN: (纸本)9781509012022

关键词： lattice-ladder neuron data flow graph FPGA implementation high level synthesis fixed-point arithmetic

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