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Integrated temporal partitioning and partial reconfiguration techniques for design latency improvement

EVOLVING SYSTEMS 2014年第2期5卷 133-141页

作者： Ayadi, Ramzi Ouni, Bouraoui Mtibaa, Abdellatif Univ Monastir Fac Sci Monastir Lab Elect & Microelect Monastir 5019 Tunisia

In this paper, we present a novel temporal partitioning methodology that temporally partitions a data flow graph on reconfigurable system. Our approach optimizes the whole latency of the design. This aim can be reached by minimizing the latency of the graph and the reconfiguration time at the same time. Consequently, our algorithm starts by an existing temporal partitioning. The existing temporal partitioning is the result of a whole latency optimization algorithm. Next, our approach builds the best architecture, on a partially reconfigurable FPGA, that gives the lowest value of reconfiguration time. The proposed methodology was tested on several examples on the Xilinx Virtex-II pro. The results show significant reduction in the design latency compared with others famous approaches used in this field.

关键词： Temporal partitioning Partially reconfigurable FPGA data flow graph VLSI applications

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Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform

Hardware Efficient VLSI Architecture for 3-D Discrete Wavele...

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27th International Conference on VLSI Design / 13th International Conference on Embedded Systems (VLSID)

作者： Darji, Anand Shukla, Saurabh Merchant, S. N. Chandorkar, A. N. Indian Inst Technol Dept Elect Engn Mumbai 400076 Maharashtra India SV Natl Inst Technol Dept Elect Engn Surat 395007 India

ISBN: (纸本)9781479925124

In this paper, a hardware efficient lifting based parallel 3-D Discrete Wavelet Transform (DWT) architecture for infinite group of pictures is proposed. Two parallel spatial and temporal DWT modules of the proposed 3-D DWT architecture give high throughput of 4 results per clock cycle. 1-D DWT blocks are employed for the spatial and temporal processing, respectively. Two parallel spatial processors reduce the requirement of frame memory for temporal transformation. Higher throughput reduces the working clock cycles which leads to low power design. A novel dual scanning in Z-fashion is utilized to reduce the internal transpose buffer requirement and waiting time of both the column and the temporal processors. The comparison results show that the internal memory requirement of the proposed 3-D DWT architecture is smaller than other familiar architectures. The Register Transfer Logic (RTL) of the proposed design is described using VHDL and synthesized for the Xilinx Virtex-IV series field programmable gate array (FPGA). The RTL of the proposed design is also synthesized using UMC 180 nm technology CMOS standard cell library for Application Specific Integrated Circuit (ASIC) design.

关键词： ASIC data flow graph Discrete Wavelet Transform FPGA Lifting VLSI Architecture

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An Application Scenario for Dynamically Reconfigurable FPGAs

An Application Scenario for Dynamically Reconfigurable FPGAs

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9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

作者： Schwiegelshohn, Fynn Huebner, Michael Ruhr Univ Bochum Chair Embedded Syst Informat Technol Bochum Germany

ISBN: (纸本)9781479958108

Several recent studies have shown the technological feasibility of dynamically reconfigurable field programmable gate arrays (FPGA). In this paper, we introduce an application scenario from the area of autonomous robots which benefits from this technology as it uses elastic algorithms. The processing unit in an autonomous robot must handle localization, cognition, motion control, and perception. We analyze several elastic algorithms which solve the different tasks of the proposed application. Additionally, we suggest a design methodology for dynamically reconfigurable FPGAs that divides the problem into several steps and addresses them separately. In the first step, compiler optimization techniques are used to generate suitable data flow graphs. Then FPGA configurations are assigned to the tasks in these graphs. Finally, the configuration sequence with the minimal amount of reconfigurations is obtained by solving a Shortest-Common-Supersequence problem.

关键词： dynamic reconfiguration FPGA Shortest-Common-Supersequence data flow graph

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Probabilistic error propagation model for mechatronic systems

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MECHATRONICS 2014年第8期24卷 1189-1202页

作者： Morozov, Andrey Janschek, Klaus Tech Univ Dresden Inst Automat D-01062 Dresden Germany

This paper addresses a probabilistic approach to error propagation analysis of a mechatronic system. These types of systems require highly abstractive models for the proper mapping of the mutual interaction of heterogeneous system components such as software, hardware, and physical parts. A literature overview reveals a number of appropriate error propagation models that are based on Markovian representation of control flow. However, these models imply that data errors always propagate through the control flow. This assumption limits their application to systems, in which components can be triggered in arbitrary order with non-sequential data flow. A motivational example, discussed in this paper, shows that control and data flows must be considered separately for an accurate description of an error propagation process. For this reason, we introduce a new concept of error propagation analysis. The central idea is a synchronous examination of two directed graphs: a control flow graph and a data flow graph. The structures of these graphs can be derived systematically during system development. The knowledge about an operational profile and properties of individual system components allow the definition of additional parameters of the error propagation model. A discrete time Markov chain is applied for the modeling of faults activation, errors propagation, and errors detection during operation of the system. A state graph of this Markov chain can be generated automatically using the discussed dual-graph representation. A specific approach to computation of this Markov chain makes it possible to obtain the probabilities of erroneous and error-free system execution scenarios. This information plays a valuable role in development of dependable systems. For instance, it can help to define an effective testing strategy, to perform accurate reliability estimation, and to speed up error detection and fault localization processes. This paper contains a comprehensive description

关键词： Control flow graph data flow graph Error propagation analysis Discrete time Markov chain Dependability UML

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SignalPU: A programming model for DSP applications on parallel and heterogeneous clusters 16

SignalPU: A programming model for DSP applications on parall...

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int Symposium on Cyberspace Safety and Security

作者： Mansouri, Farouk Huet, Sylvain Houzet, Dominique Univ Stendhal CNRS INPG UJF GIPSA Lab UMR 5216 F-38402 Grenoble France

ISBN: (纸本)9781479961238

The biomedical imagery, the numeric communications, the acoustic signal processing and many others digital signal processing (DSP) applications are present more and more in the numeric world. They process growing data volume which is represented with more and more accuracy, and use complex algorithms with time constraints to satisfying. Consequently, a high requirement of computing power characterize them. To satisfy this need, it's inevitable today to use parallel and heterogeneous architectures in order to speedup the processing, where the best examples are today's supercomputers like "Tianhe-2" and "Titan" of Top500 ranking. These architectures with their multi-core nodes supported by many-core accelerators offer a good response to this problem. However, they are still hard to program to make performance because of many reasons: Parallelism expression, task synchronization, memory management, hardware specifications handling, load balancing ... In the present work, we are characterizing DSP applications and propose a programming model based on their distinctiveness in order to implement them easily and efficiently on heterogeneous clusters.

关键词： Digital signal processing data flow graph graphic processing unit model of programming parallel and heterogenous programming Digital signal processing data flow graphs Demonstration programmes Parallel Lines graphics Processing Unit Desmoplakin Gene Programming computational power Time constraints

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Parallelization Research of Algorithm for Detecting Borders on the Basis of graph Representation 12

Parallelization Research of Algorithm for Detecting Borders ...

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12th International Conference on Actual Problems of Electronics Instrument Engineering (APEIE)

作者： Demin, A. Y. Dorofeev, V. A. Tomsk Polytech Univ Comp Sci & Engn Syst Tomsk Russia

ISBN: (纸本)9781479960200

In this paper we consider software implementation algorithm for finding the boundaries of objects in images using Sobel operator. Software implementation is presented in structural-graphical form. We propose a semi-automatic parallelization considered program load. Parallelized algorithm implemented in software product and the efficiency of parallelization was analyzed.

关键词： Sobel operator image processing tree operators data flow graph parallel programming model

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A Comparative Study of Various Object Oriented Testing Techniques

A Comparative Study of Various Object Oriented Testing Techn...

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4th International Conference on Computing, Communications and Networking Technologies (ICCCNT)

作者： Vats, Prashant Madan, Sushila Gosain, Anjana Banasthali Univ AIM & ACT Jaipur Rajasthan India Lady Shri Ram Coll New Delhi India USICT GGSIPU New Delhi India

ISBN: (纸本)9781479939251

with the invent of technology testing of OO software has become a quite tedious job. Conventional testing cannot be directly applied for testing of Object oriented programs. So, some special methodologies have been developed to test the object programs. In this paper we have enlisted few of them and their comparison is carried out. On the basis of different parameters features of OO paradigms like the Inheritance, Polymorphism, dynamic binding are main issues that have been discussed in this paper.

关键词： OOT Inheritance Polymorphism Event testing data flow graph

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Platform-independent analysis of function-level communication in workloads

Platform-independent analysis of function-level communicatio...

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IEEE International Symposium on Workload Characterization (IISWC)

作者： Nilakantan, Siddharth Hempstead, Mark Drexel Univ Dept Elect & Comp Engn Philadelphia PA 19104 USA

ISBN: (纸本)9781479905539

The emergence of many-core and heterogeneous multicore processors has meant that data communication patterns increasingly determine application performance. Microprocessor designers need tools that can extract and represent these producer-consumer relationships for a workload to aid them in a wide range of tasks including hardware-software co-design, software partitioning, and application performance optimization. This paper presents SigH, a profiling tool that can extract communication patterns within a workload independent of hardware characteristics. We show how our methodology can extract the true costs of communication within a workload by distinguishing between unique, local, and total communication. We describe the implementation and performance of SigH as well as the results of several case studies.

关键词： data flow graph data dependencies re-use partitioning critical path function

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Extending the BEAGLE library to a multi-FPGA platform

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BMC BIOINFORMATICS 2013年第1期14卷 1-11页

作者： Jin, Zheming Bakos, Jason D. Univ S Carolina Dept Comp Sci & Engn Columbia SC 29208 USA

Background: Maximum Likelihood (ML)-based phylogenetic inference using Felsenstein's pruning algorithm is a standard method for estimating the evolutionary relationships amongst a set of species based on DNA sequence data, and is used in popular applications such as RAxML, PHYLIP, GARLI, BEAST, and MrBayes. The Phylogenetic Likelihood Function (PLF) and its associated scaling and normalization steps comprise the computational kernel for these tools. These computations are data intensive but contain fine grain parallelism that can be exploited by coprocessor architectures such as FPGAs and GPUs. A general purpose API called BEAGLE has recently been developed that includes optimized implementations of Felsenstein's pruning algorithm for various data parallel architectures. In this paper, we extend the BEAGLE API to a multiple Field Programmable Gate Array (FPGA)-based platform called the Convey HC-1. Results: The core calculation of our implementation, which includes both the phylogenetic likelihood function (PLF) and the tree likelihood calculation, has an arithmetic intensity of 130 floating-point operations per 64 bytes of I/O, or 2.03 ops/byte. Its performance can thus be calculated as a function of the host platform's peak memory bandwidth and the implementation's memory efficiency, as 2.03 x peak bandwidth x memory efficiency. Our FPGA-based platform has a peak bandwidth of 76.8 GB/s and our implementation achieves a memory efficiency of approximately 50%, which gives an average throughput of 78 Gflops. This represents a similar to 40X speedup when compared with BEAGLE's CPU implementation on a dual Xeon 5520 and 3X speedup versus BEAGLE's GPU implementation on a Tesla T10 GPU for very large data sizes. The power consumption is 92 W, yielding a power efficiency of 1.7 Gflops per Watt. Conclusions: The use of data parallel architectures to achieve high performance for likelihood-based phylogenetic inference requires high memory bandwidth and a design methodology

关键词： Field Programmable Gate Array Memory Bandwidth Memory Controller Target Platform data flow graph

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A Software Function Testing Method Based on data flow graph

A Software Function Testing Method Based on Data Flow Graph

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International Symposium on Information Science and Engineering

作者： Cao, Wenjing Xu, Shenghong Naval Aeronaut & Astronaut Univ Dept Control Engn Yantai Peoples R China

ISBN: (纸本)9780769534947

Main task of function testing is to verify software function. Completion of graphic user interface (GUI) software function includes complicated human-machine interactions. Current function testing methods usually consider interface of software and environment, while ignoring software requirement and function completion process. With these testing methods, testing process may be disordered. In this paper, a function testing method based on data flow graph is proposed. Based on software requirement and interface, this method organizes function testing process with transaction processing and data flow. Comparing to the existing function testing methods, this testing method is more effective for GUI software.

关键词： software testing function testing GUI software data flow graph

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