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THROUGHPUT OPTIMIZATION BY data-flow graph TRANSFORMATION

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 1994年第11期E77A卷 1917-1921页

作者： HARASHIMA, K YOSHIDA, M KOMI, H FUKUNAGA, K Univ of Osaka Prefecture Sakai-shi Japan

We propose an optimal throughput problem using graph transformations to maximize throughput of a pipelined data path with some loops. The upper bound of the throughput, equals to the lower bound of the iteration interval between the start of two successive iterations, is limited by the length of a critical loop. Therefore we can maximize the throughput by minimizing the length of the critical loop. The proposed method first schedules an initial data flow graph (DFG) under the initial iteration interval as few as it can use resources, then it transforms the DFG into the flow graph with the minimal length of the critical loop by rescheduling the given initial scheduling result. If there are any control steps which violate the resource constraints owing to the transformations, then these operations are adjusted so as to satisfy given resource constraints. Finally by rescheduling the transformed DFG, it gives a schedule with maximum throughput. Experiments show the efficiency of our proposed approach.

关键词： HIGH LEVEL SYNTHESIS data PATH SCHEDULING data flow graph ITERATION BOUND graph TRANSFORMATION

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A recursive technique for computing lower-bound performance of schedules

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ACM Transactions on Design Automation of Electronic Systems 1996年第4期1卷 443-455页

作者： Langevin, M. Cerny, E. University of Montreal Ottawa Ont. K1Y 4H7 Canada Dép. d'Iro Université de Montréal Montréal C.P. 6128 Suce. Centre-Ville Canada

We present a fast recursive technique for estimating lower-bound performance of data path schedules. The method relies on the determination of an ASAPUC (As Soon As Possible Under Constraint) time-step value for each node of the DFG (data-flow graph) that is based on the ASAPUC values of its predecessor nodes. That is, the lower-bound estimation is applied to each subgraph permitting the derivation of a tight lower bound on the performance of the complete DFG. Applying the greedy lower-bound estimator of Rim and Jain [1994] to each subgraph improves the complete lower bound in more than 50% of the experiments reported in Rim and Jain [1994], and the CPU time is only about twice as long. The recursive methodology can be extended to exploit other lower-bound techniques, for example, considering other constraints such as the number of busses or registers. General Terms: Design, Measurement, Performance. © 1996 ACM.

关键词： data flow graph Lower-bound on performance Microcode optimization Resource constraints Scheduling

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graph transformation expert system (GTES)

Graph transformation expert system (GTES)

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4th International Conference on Computer-Aided Design and Computer graphics

作者： Li, GQ Ge, QH Zhong, L Xie, WP WUHAN UNIV TECHNOL WUHAN 430070PEOPLES R CHINA

ISBN: (纸本)0819420158

The design of many industrial and engineering systems can often be accomplished using flow graphs of various types. Examples include manufacturing processes and data processing applications, graph Transformation Expert System, is an expert system which has been developed by WUT for applying techniques of artificial intelligence to the architectural design of data and signal processing systems. Software and hardware architectures may be defined for such systems using data flow graphs, in which nodes represent data processing steps and directed areas represent the `flow' of data between the processing steps. Starting with a user- defined generic processing graphic, this expert will transform the graph by applying transformation rules in order to specialize the processing graph to satisfy specified design goals and/or hardware constraints. Although the particular application for which this expert is designed is that of data and signal processing systems, it can provide an expert system framework for other problems specified graphically; for example, manufacturing systems, information systems, and product distribution systems.

关键词： graph transformation expert system data flow graph

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A COMPUTATIONAL MODEL FOR STATIC data-flow MACHINES

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COMPUTERS & ELECTRICAL ENGINEERING 1995年第6期21卷 483-497页

作者： EASSA, FE EASSA, MM ZAKI, M Computers and Systems Engineering Department Faculty of Engineering Al-Azhar University Nasr City Cairo Egypt

Computer architects have been constantly looking for new approaches to design high-performance machines. data flow and VLSI offer two mutually supportive approaches towards a promising design for future super-computers. When very high speed computations are needed, data flow machines may be relied upon as an adequate solution in which extremely parallel processing is achieved. This paper presents a formal analysis for data flow machines. Moreover, the following three machines are considered: (1) MIT static data flow machine;(2) TI's DDP static data flow machine;(3) LAU data flow machine. These machines are investigated by making use of a reference model. The contributions of this paper include: (1) Developing a data flow Random Access Machine model (DFRAM), for first time, to serve as a formal modeling tool. Also, by making use of this model one can calculate the time cost of various static data machines, as well as the performance of these machines. (2) Constructing a practical data flow Simulator (DFS) on the basis of the DFRAM model. Such DFS is modular and portable and can be implemented with less sophistication. The DFS is used not only to study the performance of the underlying data flow machines but also to verify the DFRAM model.

关键词： STATIC data flow MACHINE PARALLEL PROCESSING COMPUTER ARCHITECTURE RANDOM ACCESS MACHINE MODEL data flow RANDOM ACCESS MACHINE MODEL data flow graph FIRING TIME TAKEN TABLE QUEUE STRUCTURE ENABLING NETWORK CONTROLLER

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MIXED ANALOG-DIGITAL HARDWARE SYNTHESIS OF ARTIFICIAL NEURAL NETWORKS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1994年第9期13卷 1073-1087页

作者： ACHYUTHAN, A ELMASRY, MI UNIV WATERLOO DEPT ELECT & COMP ENGNVLSI RES GRPWATERLOO N2L 3G1ONTARIOCANADA

A methodology for automated synthesis of mixed analog/digital hardware architectures for Artificial Neural Network (ANN) applications is presented. The ANN system is input in the form of a data flow graph (DFG) of operators. The output is a high-level interconnection description of mixed analog/digital building block circuits that is generated by searching a multidimensional design space to satisfy the throughput requirements and minimize an area-time cost function. A combination of quantitative analysis and behavioral modeling techniques tackles the problems of hardware nonidealities by screening suitable analog circuits. Digital hardware is employed when no analog circuit is found that satisfies the performance requirements of any operation. A heuristic partitioning scheme reduces the interfaces between blocks of circuits operating in analog and digital modes. The parallelism in ANN systems is handled by a new scheduling and allocating procedure that selectively sequentializes groups of operations with the goal of iteratively improving an area-time cost function. The synthesizer is also capable of embedding hardware units that are intended to operate asynchronously. The synthesis methodology is illustrated with two design examples.

关键词： ANALOG CIRCUIT NONIDEALITIES ARTIFICIAL NEURAL NETWORKS BEHAVIORAL MODELING data flow graph HIGH-LEVEL SYNTHESIS MIXED ANALOG DIGITAL SYSTEM

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A 2-PASS SCHEDULING ALGORITHM FOR PARALLEL PROGRAMS

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PARALLEL COMPUTING 1994年第6期20卷 869-885页

作者： KIM, DS YI, BG Department of Computer Science Pohang University of Science and Technology P.O. Box 125 Pohang 790-600 South Korea B.-G. Yi is currently with POSCON Pohang Korea

In this paper a fast task scheduling algorithm is proposed. An optimal task scheduling assigns tasks to processors such that the overall completion time (makespan) of a given task is minimized. To find an optimal task scheduling is known NP-complete. The proposed algorithm finds a suboptimal solution in 0(n log n) time, where n is the number of nodes in the task graph. Experimental results reveal the fact that the algorithm produces a good scheduling output several thousand times faster, whose makespan is longer by 5% at worst, than simulated annealing.

关键词： PROCESSOR SCHEDULING NONPREEMPTIVE SCHEDULING data flow graph INTERPROCESSOR COMMUNICATION COMPILER PARALLEL COMPUTER

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TEST-GENERATION FROM LOTOS SPECIFICATIONS

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IEEE TRANSACTIONS ON COMPUTERS 1991年第4期40卷 543-552页

作者： TRIPATHY, P SARIKAYA, B UNIV MONTREAL DEPT INFORMAT & RECH OPERATMONTREAL H3C 3J7QUEBECCANADA

A new approach is proposed to generate test cases from LOTOS specifications for protocol conformance testing. A set of transformation rules is applied to the specification. Then the specification is mapped to an extended finite state machine called chart. The flow of data in the chart is modeled by a data flow graph. Test cases are generated from the chart. Program testing strategies are applied for test case selection. A tool implementing this methodology on a workstation is also discussed.

关键词： ABSTRACT data TYPE CHART CONFORMANCE TESTING data flow graph FUNCTIONAL ANALYSIS LOTOS PROCESS ALGEBRA TEST CASE TRANSITION SYSTEM

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ON THE ANALYSIS AND OPTIMIZATION OF SELF-TIMED PROCESSOR ARRAYS

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INTEGRATION-THE VLSI JOURNAL 1991年第2期12卷 167-187页

作者： THIELE, L Institute of Microelectronics University of Saarland D-6600 Saarbrücken Germany

The paper deals with systematic methods for analyzing and designing selftimed regular arrays of processors. Methods are presented for deriving measures of efficiency and for verifying the computational behavior of a given array. It is shown that the optimization of a given regular selftimed processor array, with respect to its processor utilization, can be given mathematically in the form of linear programs or integer linear programming problems, whose sizes are independent of the size of the array.

关键词： PROCESSOR ARRAY PARALLEL PROCESSING data flow graph

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FROM BAREISS ALGORITHM TO THE STABLE COMPUTATION OF PARTIAL CORRELATIONS

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JOURNAL OF COMPUTATIONAL AND APPLIED MATHEMATICS 1989年第1-2期27卷 53-91页

作者： DELOSME, JM IPSEN, ICF YALE UNIV DEPT ELECT ENGNNEW HAVENCT 06520 YALE UNIV DEPT COMP SCINEW HAVENCT 06520

This paper presents a new algorithm for the stable computation of sample partial correlation coefficients. We start by generalizing Bareiss' algorithm for the solution of linear systems of equations with (non-symmetric) Toeplitz coefficient matrix to matrices that are not Toeplitz, and show that it computes their LU and UL factorizations. For symmetric positive-definite matrices B , the normalized version of Bareiss' algorithm is the Hyperbolic Cholesky algorithm, which computes the upper and lower triangular Cholesky factors U and L of B by means of 2×2 hyperbolic rotations. If B is a convariance matrix, certain partial correlation coefficients may be obtained as the geometric means of the multiplier pairs in Bareiss' algorithm or as the hyperbolic tangents of the hyperbolic rotations. The partial correlation coefficients for a given data matrix A may suffer from serious loss of numerical accuracy when computed from the covariance matrix B = A T A . While the data flow graph of Bareiss' algorithm suggests a method, due to Cybenko, for computing partial correlation coefficients directly from the columns of A , the graph of Hyperbolic Cholesky suggests an alternative that requires fewer operations nd exhibits a higher degree of parallelism. In that method one computes the QR decomposition A = QU of the data matrix and applies orthogonal rotations to transform U to L ; the sines of the rotation angles constitute a set of partial correlation coefficients. We extend this approach to determine arbitrary partial correlation coefficients at little extra computational cost.

关键词： LU factorization Cholesky factorization partial correlation coefficients parallel computation data flow graph hyperbolic rotations Givens rotations Toeplitz matrices

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THE PARTITIONING OF QSDF COMPUTATION graphS

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PARALLEL COMPUTING 1989年第3期9卷 347-358页

作者： GOTTLIEB, I Department of Computer Science Bar Ilan University Tel Aviv Israel

In a previous paper the Quasi Synchronous data flow (QSDF) model of computation was presented. A data flow graph is partitioned into disjoint directed paths, called computation paths, with the object of permitting a processor to execute along such a path in a sequential manner as far as possible. Such sequential execution will be facilitated to the extent that each operator along the path, when encountered by the executing processor, will have been supplied with any operand(s) it may require from nodes on other computation paths. If such is found not to be the case, execution of the path must be suspended and will be resumed at such time as the operand arrives. In this paper, the question of how best to effect such a partition is addressed. A definition of optimality under the QSDF execution discipline is obtained and a closed form for the value of the cardinality of the partition is derived. An algorithm for obtaining an optimal partition is presented and some properties of the resulting partition are examined. Only static program behavior is considered in the analysis.

关键词： Parallel processing data flow graph Quasi Synchronous data flow (QSDF) model optimal partitioning of static program structure

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