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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Yu, Jintao Nane, Razvan Haron, Adib Hamdioui, Said Corporaal, Henk Bertels, Koen Delft Univ Technol Mekelweg 4 NL-2628 CD Delft Netherlands Eindhoven Univ Technol Postbus 513 NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781450343305

Memristor-based Computation-in-Memory is one of the emerging architectures proposed to deal with Big data problems. The design of such architectures requires a radically new automatic design flow because the memristor is a passive device that uses resistance to encode its logic value. This paper proposes a design flow for mapping parallel algorithms on the CIM architecture. Algorithms with similar data flow graphs can be mapped on the crossbar using the same template containing scheduling, placement, and routing information;this template is named skeleton. By configuring such a skeleton with different pre-designed circuits, we can build CIM implementations of the corresponding algorithms in that class. This approach does not only map an algorithm on a memristor crossbar, but also gives an estimation of its performance, area, and energy consumption. It also supports user-defined constraints and parallel SystemC simulation. Experimental results demonstrate the feasibility and the potential of the approach.

关键词： data flow graphs

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Design of low power based VLSI architecture for constant multiplier and high speed implementation using retiming technique

Design of low power based VLSI architecture for constant mul...

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2016 International Conference on Microelectronics, Computing and Communication, MicroCom 2016

作者： Jalaja, S. Prakash, A. M. Vijaya Dept. of Electronics and Communication Engg. Bangalore Institute of Technology Bangalore India

ISBN: (纸本)9781467366212

This paper comprises of new low power multiplication algorithm and VLSI architecture. The one less than previous is foundation to built the proposed algorithm. The algorithm is simple straightforward to find NxN unsigned binary number multiplication using 2n-1 constant number which is used recursively for both multiplicand and multiplier. It revealed that reusability of the hardware resource results low power consumption and better power delay product compared to conventional multiplier. Apply the knowledge of data flow graph for the mathematical expression of the proposed algorithm to construct a set of hardware block. The performance of the 256 bit multiplication yields a savings of 46.34% in power and 47.5% in power delay product over the existing conventional multiplier. Further, the art of optimization technique, like retiming approach is adopted to design fast multiplication. The proposed algorithm with retiming analysis results are compared with conventional multiplier as well as constant multiplier. The functional verification and sythesization of the proposed architecture is analyzed using cadence EDA tools and implemented using 45nm technology libraries. The retiming approach for the proposed algorithm gives 86.9% in power delay product compared to conventional method and a reduction of 75.05% in power delay product over the proposed work. © 2016 IEEE.

关键词： data flow graphs

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Polyhedral optimizations for a data-flow graph language 28th

Polyhedral optimizations for a data-flow graph language

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28th International Workshop on Languages and Compilers for Parallel Computing, LCPC 2015

作者： Sbîrlea, Alina Shirako, Jun Pouchet, Louis-Noël Sarkar, Vivek Rice University Houston United States Ohio State University Columbus United States

ISBN: (纸本)9783319297774

This paper proposes a novel optimization framework for the data-flow Graph Language (DFGL), a dependence-based notation for macro-dataflow model which can be used as an embedded domain-specific language. Our optimization framework follows a "dependence-first" approach in capturing the semantics of DFGL programs in polyhedral representations, as opposed to the standard polyhedral approach of deriving dependences from access functions and schedules. As a first step, our proposed framework performs two important legality checks on an input DFGLprogram—checking for potential violations of the single-assignment rule, and checking for potential deadlocks. After these legality checks are performed, the DFGL dependence information is used in lieu of standard polyhedral dependences to enable polyhedral transformations and code generation,which include automatic loop transformations, tiling, and code generation of parallel loops with coarse-grain (fork-join) and fine-grain (doacross) synchronizations. Our performance experiments with nine benchmarks on IntelXeon andIBMPower7multicore processors showthat theDFGL versions optimized by our proposed framework can deliver up to 6.9× performance improvement relative to standard OpenMP versions of these benchmarks. To the best of our knowledge, this is the first system to encode explicit macro-dataflow parallelism in polyhedral representations so as to provide programmers with an easy-to-use DSL notation with legality checks, while taking full advantage of the optimization functionality in state-of-the-art polyhedral frameworks. © Springer International Publishing Switzerland 2016.

关键词： data flow graphs

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Deep ADMM-Net for Compressive Sensing MRI 16

Deep ADMM-Net for Compressive Sensing MRI

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Annual Conference on Neural Information Processing Systems

作者： Yan Yang Huibin Li Jian Sun Zongben Xu Xi'an Jiaotong University

ISBN: (纸本)9781510838819

Compressive Sensing (CS) is an effective approach for fast Magnetic Resonance Imaging (MRI). It aims at reconstructing MR image from a small number of under- sampled data in k-space, and accelerating the data acquisition in MRI. To improve the current MRI system in reconstruction accuracy and computational speed, in this paper, we propose a novel deep architecture, dubbed ADMM-Net. ADMM- Net is defined over a data flow graph, which is derived from the iterative procedures in Alternating Direction Method of Multipliers (ADMM) algorithm for optimizing a CS-based MRI model. In the training phase, all parameters of the net, e.g., image transforms, shrinkage functions, etc., are discriminatively trained end-to-end using L-BFGS algorithm. In the testing phase, it has computational overhead similar to ADMM but uses optimized parameters learned from the training data for CS-based reconstruction task. Experiments on MRI image reconstruction under different sampling ratios in k-space demonstrate that it significantly improves the baseline ADMM algorithm and achieves high reconstruction accuracies with fast computational speed.

关键词： Magnetic Resonance Imaging C7orf49 gene data flow graphs Compressed sensing data sampling image reconstruction data Collection Methods Reconstructive Surgical Procedures

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A novel framework for retiming using evolutionary computation for high level synthesis of digital filters

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SWARM AND EVOLUTIONARY COMPUTATION 2015年 20卷 37-47页

作者： Yagain, Deepa Vijayakrishna, A. PESIT Dept ECE Bangalore Karnataka India

In this paper, design of a new algorithm and a framework for retiming the DSP blocks based on evolutionary computation process is explained. Optimal DSP blocks such as digital filter design is a high level synthesis problem which includes optimally mapping digital filter specifications on to FPGA (Field Programmable Gate Array) architecture. Retiming is the considered optimization method in this paper which gives optimality in terms of algorithm processing speed and digital filter operating frequency with register count as a constraint. The designed novel algorithm is for the synthesis of high speed digital filters for different signal processing applications based on nature inspired evolutionary computation method. The classical retiming algorithms such as clock period minimization and register minimization that are addressed in the literature provide a single heuristic solution based on the chosen optimization parameter such as clock period. However, for retiming which is multi-objective optimization, evolutionary approach can lead to better results. Using the designed evolutionary computation based retiming method, retimed solution database is generated with higher frequency and different output register counts by searching the digital block solution space. Depending on the clock period and register count constraint, designer can take a design decision. Here, various signal processing designs are used to facilitate the design analysis. Results also show that the CPU processing time needed to compute multiple solutions using the designed algorithm for filter circuits is reduced for designs whose maximum feasible solutions are less than 50. If the circuit is very big with the possible solution space greater than 50 solutions, then algorithm performs slower. A comparison is also provided in the Simulations section with respect to all the existing classical retiming methods in the literature such as clock period and register minimization retiming to prove the concept

关键词： Solution space Tournament selection Digital filter optimization Retiming data flow graphs Non-dominated Sorting Genetic Algorithm (NSGA)

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Program Slicing Based on Runtime dataflow Measurements 16

Program Slicing Based on Runtime Dataflow Measurements

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16th International Carpathian Control Conference (ICCC)

作者： Wacha, Gabor Lazanyi, Janos Feher, Bela Budapest Univ Technol & Econ Dept Measurement & Informat Technol Budapest Hungary

ISBN: (纸本)9781479973705

Multicore architectures enable increasing the performance of the system with parallel processing. One of the challenges of a multicore embedded system is the correct usage of the processor cores. It is possible to achieve balanced processor load on the different cores, but the communication bandwidth between the cores is often a bottleneck. Passing large amounts of data between tasks mapped to different processor cores can result in cache misses in the local cache of a processor core. This paper introduces an analyzation method based on runtime generated data flow graphs to find the data paths of an algorithm. It shows that a spectral cluster analysis can help to discover data independent subsets in the algorithm under test. Finding the data independent parts helps to partition the program to multiple slices where the inter-slice communication is kept as low as possible. With our proposed method the communication bottleneck can be evaded in a multicore, multitask implementation, possibly resulting in better performance.

关键词： Processor Core program slicing Runtime core Multi-core processors Core samples data flow graphs channels (data transmission) Traffic Bottlenecks PROCESSOR data flow PARALLEL PROCESSING (COMPUTERS) Cache memory Communication Research

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Resource-saving compile flow for coarse-grained reconfigurable architectures

Resource-saving compile flow for coarse-grained reconfigurab...

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International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015

作者： Zhao, Zhongyuan Sheng, Weiguang Jing, Naifeng He, Weifeng Mao, Zhigang Department of Micro/NaNo Electronics Shanghai Jiao Tong University Shanghai China

ISBN: (纸本)9781467394062

Coarse-Grained Reconfigurable Architectures (CGRA) are promising accelerators with high performance and power-efficiency. Most compilers map loop kernels of the compute-intensive applications onto CGRA through modified modulo scheduling algorithms. EPIMap converts the problem into finding a subgraph of time extend CGRA that matches modified data flow graph (DFG). Therefore, the number of nodes and edges in the final modified DFG decides the resources used in time extend CGRA, thus influence the performance. To this end, it is essential to find an effective way reducing nodes and edges in the modified DFG to save the resources in time extend CGRA. Besides, existing compilers lack a systematic way to modify DFG. To address these problems, this paper firstly choose to use a new CGRA with global synchronization mechanism, which help reducing the nodes and edges in modified DFG. Secondly, proposing a complete and systematic DFG modification flow which saves more resources. Finally, to reduce the compile time, a resource-monitoring mapping heuristic with lower time complexity is provided. The experiment result shows that our global synchronized CGRA can save at most 17% computing and routing resources compared with general CGRA, our DFG modifying flow can save at most 20% computing and routing resources compared with EPIMap. Besides, our resource-saving compile flow generate performance as good as EPIMap while taking less compile time. © 2015 IEEE.

关键词： data flow graphs

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Optimizing data- flow graphs with Min/Max, Adding and Relational Operations

Optimizing Data- Flow Graphs with Min/Max, Adding and Relati...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Perez, J. Sanchez, P. Fernandez, V. Univ Cantabria TEISA GIM Santander Spain

ISBN: (纸本)9783981080162

During Electronic System-Level (ESL) design, HighLevel Synthesis (HLS) tools normally translate the system description to a Control/data flow Graph. At this level, several transformations are performed as early as possible to reduce the number and complexity of the data operations. These preliminary transformations (for example, common sub-expression elimination, constant propagation, etc) are typically applied in algebraic expressions with arithmetic operators. This paper presents preliminary transformations that optimize data-flow graphs with relational, maximum/minimum and arithmetic (addition/subtraction) operations. The proposed techniques produce a significant reduction in the number of operations. HLS tools and even software compilers and symbolic algebra packages are not able to generate similar results. The efficiency of the techniques has been evaluated with several modules of real telecommunications standards and their HW implementations show important area reductions and, sometimes, low impact on latency or critical path.

关键词： data flow graphs

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System-level Scheduling of Real-time Streaming Applications using a Semi-partitioned Approach

System-level Scheduling of Real-time Streaming Applications ...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Cannella, Emanuele Bamakhrama, Mohamed A. Stefanov, Todor Leiden Univ Leiden Inst Adv Comp Sci Leiden Netherlands

ISBN: (纸本)9783981537024

Modern multiprocessor streaming systems have hard real-time constraints that must be always met to ensure correct functionality. At the same time, these streaming systems must be designed to use the minimum required amount of resources (such as processors and memory). In order to meet such constraints, using scheduling algorithms from the classical real-time scheduling theory represents an attractive solution approach. These algorithms enable: (1) providing timing guarantees to the applications running on the system, and (2) deriving analytically the minimum number of processors required to schedule the applications. So far, designers in the embedded systems community have focused on global and partitioned scheduling algorithms. However, recently, a new hybrid class of scheduling algorithms has been proposed. In this work, we investigate the applicability of a sub-class of these hybrid algorithms, called semi-partitioned algorithms, to applications modeled as Cyclo-Static dataflow (CSDF) graphs. The contribution of this paper is two fold. First, we devise an approach that enables semi-partitioned scheduling algorithms, even soft real-time ones, to be applied to CSDF graphs while providing hard real-time guarantees at the input/output interfaces with the external environment. Second, we focus on an existing soft real-time semi-partitioned approach, for which we propose an allocation heuristic, called FFD-SP. The proposed heuristic reduces the minimum number of processors required to schedule the applications compared to a pure partitioned scheduling algorithm, while trying to minimize the buffer size and latency increases incurred by the soft real-time approach.

关键词： data flow graphs embedded systems integrated circuit design multiprocessing systems processor scheduling FFD-SP allocation heuristic cyclo static data flow graph embedded systems multiprocessor streaming systems real time streaming scheduling algorithms semipartitioned algorithm system level scheduling timing guarantee Equations Partitioning algorithms Program processors Real-time systems Schedules Scheduling algorithms

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Insider Attack Identification and Prevention Using a Declarative Approach

Insider Attack Identification and Prevention Using a Declara...

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35th IEEE-Computer-Society Workshop on Security and Privacy (SP)

作者： Sarkar, Anandarup Kohler, Sven Riddle, Sean Ludascher, Bertram Bishop, Matt Univ Calif Davis Davis CA 95616 USA

ISBN: (纸本)9781479951031

A process is a collection of steps, carried out using data, by either human or automated agents, to achieve a specific goal. The agents in our process are insiders;they have access to different data and annotations on data moving in between the process steps. At various points in a process, they can carry out attacks on privacy and/or security of the process through their interactions with different data and annotations, via the steps which they control. These attacks are sometimes difficult to identify as the rogue steps are hidden among the majority of the usual non-malicious steps of the process. We define process models and attack models as dataflow-based directed graphs. An attack A is successful on a process P if there is a mapping relation from A to P that satisfies a number of conditions. These conditions encode the idea that an attack model needs to have a corresponding similarity match in the process model to be successful. We propose a declarative approach to vulnerability analysis. We encode the match conditions using a set of logic rules that define what a valid attack is. Then we implement an approach to generate all possible ways in which agents can carry out a valid attack A on a process P, thus informing the process modeler of vulnerabilities in P. The agents, in addition to acting by themselves, can also collude to carry out an attack. Once A is found to be successful against P, we automatically identify improvement opportunities in P and exploit them, eliminating ways in which A can be carried out against it. The identification uses information about which steps in P are most heavily attacked, and try to find improvement opportunities in them first, before moving onto the lesser attacked ones. We then evaluate the improved P to check if our improvement is successful. This cycle of process improvement and evaluation iterates until A is completely thwarted in all possible ways.

关键词： computer crime cryptography data flow graphs data privacy directed graphs logic programming attack model data flow based directed graphs declarative approach improvement opportunities insider attack identification insider attack prevention logic rules mapping relation nonmalicious steps privacy process models security similarity match vulnerability analysis data models Diamonds Impedance matching Nominations and elections Process control Robustness Security Declarative Programming Process Modeling Vulnerability Analysis procedural model data flow graphs directed graphs Computer crime data privacy data models impedance matching Logic programming Privacy diamonds Security Process control cryptography Declarative Programming Phosphorus

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