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检索条件"主题词=Data Flow Graphs"

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dataflow programming using AGAPIA 13

Dataflow programming using AGAPIA

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13th IEEE International Symposium on Parallel and Distributed Computing (ISPDC)

作者： Paduraru, Ciprian I. Univ Bucharest Dept Comp Sci Bucharest Romania

ISBN: (纸本)9781479959198

As distributed applications became more commonplace and more sophisticated, new programming languages and models for distributed programming were created. In the context of continuously increasing data flows in parallel applications, there is a renewed interest in the dataflow paradigm. This paper shows why AGAPIA language is suitable for dataflow programming. AGAPIA is capable of expressing massive parallelism in a manageable way for programmers, allowing building dynamic nodes and links in the data flow graph at runtime. The nodes of the dataflow graph, also called programs, are modular and reusable. The communication is transparent for users allowing them to concentrate on the high level flow and algorithm. A complete application and an analysis in terms of productivity and performance are presented in order to demonstrate the AGAPIA's capabilities.

关键词： Arrays Computer languages Parallel processing Programming Runtime Silicon Syntactics Computer Programming Languages Runtime Programming PARALLEL PROCESSING (COMPUTERS) data flow Silicon data flow graphs arrays Distributed software Computer personnel

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SignalPU: A programming model for DSP applications on parallel and heterogeneous clusters 16

SignalPU: A programming model for DSP applications on parall...

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16th IEEE Int Conf on High Performance Computing and Communications/11th IEEE Int Conf on Embedded Software and Systems\6th Int Symposium on Cyberspace Safety and Security

作者： Mansouri, Farouk Huet, Sylvain Houzet, Dominique Univ Stendhal CNRS INPG UJF GIPSA Lab UMR 5216 F-38402 Grenoble France

ISBN: (纸本)9781479961238

The biomedical imagery, the numeric communications, the acoustic signal processing and many others digital signal processing (DSP) applications are present more and more in the numeric world. They process growing data volume which is represented with more and more accuracy, and use complex algorithms with time constraints to satisfying. Consequently, a high requirement of computing power characterize them. To satisfy this need, it's inevitable today to use parallel and heterogeneous architectures in order to speedup the processing, where the best examples are today's supercomputers like "Tianhe-2" and "Titan" of Top500 ranking. These architectures with their multi-core nodes supported by many-core accelerators offer a good response to this problem. However, they are still hard to program to make performance because of many reasons: Parallelism expression, task synchronization, memory management, hardware specifications handling, load balancing ... In the present work, we are characterizing DSP applications and propose a programming model based on their distinctiveness in order to implement them easily and efficiently on heterogeneous clusters.

关键词： Digital signal processing data flow graph graphic processing unit model of programming parallel and heterogenous programming Digital signal processing data flow graphs Demonstration programmes Parallel Lines Graphics Processing Unit Desmoplakin Gene Programming computational power Time constraints

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A data flow Graph Generation Method Starting from C Description by Handling Loop Nest Hierarchy

A Data Flow Graph Generation Method Starting from C Descript...

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9th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI)

作者： Arato, Peter Suba, Gergely Budapest Univ Technol & Econ Dept Control Engn & Informat Technol H-1117 Budapest Hungary

ISBN: (纸本)9781479946945

The system-level synthesis of complex hardware or multiprocessing systems starts from some kind of a task description formalized usually in a high-level programming language. For this purpose, the C language is used very often. The further steps of the synthesis procedure are based on some kind of data flow graph representation of the task. Therefore, transforming C-code into a graph representation (as systematic as possible) is crucial step in the whole synthesis procedure. One of the difficulty in formalizing transformation algorithm is that the C-code may contain nested loops. The existing solutions suffer from the difficulty of handling such loop nest hierarchy. We present a method, which can solve systematically the transformation from the C-code into a multi-rate data flow graph representation by handling the nested loops. The main steps of the method are illustrated by a simple example.

关键词： data flow graphs C CODES Graph representations Loops Handling (Psychology) high-level programming languages Multiprocessing systems C language Social Hierarchy nests Contraceptive Coil

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Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems

Just-In-Time Scheduling Techniques for Multicore Signal Proc...

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IEEE Global Conference on Signal and Information Processing (GlobalSIP)

作者： Heulot, Julien Pelcat, Maxime Nezan, Jean-Francois Oliva, Yaset Aridhi, Slaheddine Bhattacharyya, Shuvra S. UEB INSA Rennes IETR CNRSUMR 6164 Rennes France Univ Maryland College Pk MD USA Texas Instruments France Cagnes Sur Mer France

ISBN: (纸本)9781479970889

This paper introduces a novel multicore scheduling method that leverages a parameterized dataflow Model of Computation (MoC). This method, which we have named Just-In-Time Multicore Scheduling (JIT-MS), aims to efficiently schedule Parameterized and Interfaced Synchronous dataflow (PiSDF) graphs on multicore architectures. This method exploits features of PiSDF to find locally static regions that exhibit predictable communications. This paper uses a multicore signal processing benchmark to demonstrate that the JIT-MS scheduler can exploit more parallelism than a conventional multicore task scheduler based on task creation and dispatch. Experimental results of the JIT-MS on an 8-core Texas Instruments Keystone Digital Signal Processor (DSP) are compared with those obtained from the OpenMP implementation provided by Texas Instruments. Results shows latency improvements of up to 26% for multicore signal processing systems.

关键词： data flow graphs digital signal processing chips multiprocessing systems parallel architectures processor scheduling 8-core Texas Instruments keystone digital signal processor DSP JIT-MS scheduler MoC OpenMP implementation PiSDF just-in-time multicore scheduling just-in-time scheduling techniques locally static regions multicore architectures multicore scheduling method multicore signal processing systems multicore task scheduler parameterized and interfaced synchronous dataflow graphs parameterized dataflow model of computation Benchmark testing Finite impulse response filters Multicore processing Processor scheduling Scheduling Signal processing algorithms

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Memory-Constrained Static Rate-Optimal Scheduling of Synchronous dataflow graphs via Retiming

Memory-Constrained Static Rate-Optimal Scheduling of Synchro...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Zhu, Xue-Yang Geilen, Marc Basten, Twan Stuijk, Sander Chinese Acad Sci State Key Lab Comp Sci Inst Software Beijing 100190 Peoples R China Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9783981537024

Synchronous dataflow graphs (SDFGs) are widely used to model digital signal processing (DSP) and streaming media applications. In this paper, we use retiming to optimize SDFGs to achieve a high throughput with low storage requirement. Using a memory constraint as an additional enabling condition, we define a memory constrained self-timed execution of an SDFG. Exploring the state-space generated by the execution, we can check whether a retiming exists that leads to a rate-optimal schedule under the memory constraint. Combining this with a binary search strategy, we present a heuristic method to find a proper retiming and a static scheduling which schedules the retimed SDFG with optimal rate (i. e., maximal throughput) and with as little storage space as possible. Our experiments are carried out on hundreds of synthetic SDFGs and several models of real applications. Di ff erential synthetic graph results and real application results show that, in 79% of the tested models, our method leads to a retimed SDFG whose rate-optimal schedule requires less storage space than the proven minimal storage requirement of the original graph, and in 20% of the cases, the returned storage requirements equal the minimal ones. The average improvement is about 7.3%. The results also show that our method is computationally e ffi cient.

关键词： data flow graphs directed graphs heuristic programming scheduling search problems DSP SDFGs binary search strategy differential synthetic graph digital signal processing heuristic method media streaming memory constrained self-timed execution memory-constrained static rate-optimal scheduling static scheduling storage space synchronous dataflow graphs via retiming Computational modeling Delays Digital signal processing Memory management Schedules Throughput Vectors

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Buffer Allocation for Real-Time Streaming on a Multi-Processor without Back-Pressure 12

Buffer Allocation for Real-Time Streaming on a Multi-Process...

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12th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia)

作者： Salunkhe, Hrishikesh Moreira, Orlando van Berkelv, Kees Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Ericsson BV Eindhoven Eindhoven Netherlands

ISBN: (纸本)9781479963072

The goal of buffer allocation for real-time streaming applications, modeled as dataflow graphs, is to minimize total memory consumption while reserving sufficient space for each production without overwriting any live tokens and guaranteeing the satisfaction of real-time constraints. We present a buffer allocation solution for dataflow graphs scheduled on a system without back-pressure. Our contributions are 1) We extend the available dataflow techniques by applying best-case analysis. 2) We introduce dominator based relative life-time analysis. For our benchmark set, it exhibits up to 12% savings on memory consumption compared to traditional absolute life-time analysis. 3) We investigate the effect of variation in execution times on the buffer sizes for systems without back-pressure. It turns out that reducing the variation in execution times reduces the buffer sizes. 4) We compare the buffer allocation techniques for systems with and without back-pressure. For our benchmark set, we show that the system with back-pressure reduces the total memory consumption by as much as 28 % compared to the system without back-pressure. Our benchmark set includes wireless communications and multimedia applications.

关键词： buffer storage constraint satisfaction problems data flow graphs media streaming multiprocessing systems real-time systems backpressure buffer allocation solution buffer allocation techniques dataflow graphs dominator based relative life-time analysis multimedia applications multiprocessor real-time constraint satisfaction real-time streaming applications total memory consumption minimization wireless communications Delays Equations Mathematical model Memory management Real-time systems Resource management real-time systems Multiprocessor buffer allocation BACK PRESSURE MULTIMEDIA APPLICATION data flow graphs Multiprocessing systems CARRIER SYSTEM media streaming BUFFER STORAGE Store management constraint satisfaction problems management of resources Mathematical Model BENCHMARKS

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SDG2KPN: System Dependency Graph to Function-level KPN generation of Legacy Code for MPSoCs

SDG2KPN: System Dependency Graph to Function-level KPN gener...

引用

19th Asia and South Pacific Design Automation Conference (ASP-DAC)

作者： Ambrose, Jude Angelo Peddersen, Jorgen Parameswaran, Sri Labios, Alvin Yachide, Yusuke Univ New S Wales Sch Comp Sci & Engn Sydney NSW 2052 Australia Canon Informat Syst Res Australia N Ryde NSW Australia

ISBN: (纸本)9781479928163

The Multiprocessor System-on-Chip (MPSoC) paradigm as a viable implementation platform for parallel processing has expanded to encompass embedded devices. The ability to execute code in parallel gives MPSoCs the potential to achieve high performance with low power consumption. In order for sequential legacy code to take advantage of the MPSoC design paradigm, it must first be partitioned into data flow graphs (such as Kahn Process Networks - KPNs) to ensure the data elements can be correctly passed between the separate processing elements that operate on them. Existing techniques are inadequate for use in complex legacy code. This paper proposes SDG2KPN, a System Dependency Graph to KPN conversion methodology targeting the conversion of legacy code. By creating KPNs at the granularity of the function-/procedure-level, SDG2KPN is the first of its kind to support shared and global variables as well as many more program patterns/application types. We also provide a design flow which allows the creation of MPSoC systems utilizing the produced KPNs. We demonstrate the applicability of our approach by retargeting several sequential applications to the Tensilica MPSoC framework. Our system parallelized AES, an application of 950 lines, in 4.8 seconds, while H.264, of 57896 lines, took 164.9 seconds to parallelize.

关键词： data flow graphs

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Sound and soundness: Practical total functional data-flow programming

Sound and soundness: Practical total functional data-flow pr...

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2nd ACM SIGPLAN International Workshop on Functional Art, Music, Modelling and Design, FARM 2014

作者： Trancón Y Widemann, Baltasar Lepper, Markus Ilmenau University of Technology Ilmenau Germany Semantics GmbH Berlin Germany

ISBN: (纸本)9781450330398

The field of declarative data-stream programming (discrete time, clocked synchronous, compositional, data-centric) is divided between the visual data-flow graph paradigm favored by domain experts, the functional reactive paradigm favored by academics, and the synchronous paradigm favored by developers of low-level systems. Each approach has its particular theoretical and practical merits and target audience. The programming language Sig has been designed to unify the underlying paradigms in a novel way. The natural expressivity of visual approaches is combined with the support for concise pattern-based symbolic computation of functional programming, and the rigorous, elementary semantical foundation of synchronous approaches. Here we demonstrate the current state of implementation of the Sig system by means of example programs that realize typical components of digital sound synthesis. © 2014 Authors.

关键词： data flow graphs

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Foundations of total functional data-flow programming 5

Foundations of total functional data-flow programming

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5th Workshop on Mathematically Structured Functional Programming, MSFP 2014

作者： Trancón Y Widemann, Baltasar Lepper, Markus Ilmenau University of Technology de Germany GmbH de Germany

The field of declarative stream programming (discrete time, clocked synchronous, modular, datacentric) is divided between the data-flow graph paradigm favored by domain experts, and the functional reactive paradigm favored by academics. In this paper, we describe the foundations of a framework for unifying functional and data-flow styles that differs from FRP proper in significant ways: It is based on set theory to match the expectations of domain experts, and the two paradigms are reduced symmetrically to a low-level middle ground, with strongly compositional semantics. The design of the framework is derived from mathematical first principles, in particular coalgebraic coinduction and a standard relational model of stateful computation. The abstract syntax and semantics introduced here constitute the full core of a novel stream programming language.

关键词： data flow graphs

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Optimizing data flow graphs to Minimize Hardware Implementation

Optimizing Data Flow Graphs to Minimize Hardware Implementat...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Gomez-Prado, D. Ren, Q. Ciesielski, M. Guillot, J. Boutillon, E. Univ Massachusetts ECE Dept Amherst MA 01003 USA European Univ Bretagne Univ Bretagne Sud CNRS LAB STICC Rennes France

ISBN: (纸本)9781424437818

This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain. Experimental results show that the DFGs generated from such optimized expressions are better suited for high level synthesis, and the final, scheduled implementations are characterized, on average, by 15.5% lower latency and 7.6% better area than those obtained using traditional CSE and algebraic decomposition.

关键词： data flow graphs

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