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检索条件"主题词=Data Flow Graphs"

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Automatic Enhanced CDFG Generation based on Runtime Instrumentation

Automatic Enhanced CDFG Generation based on Runtime Instrume...

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IEEE 17th International Conference on Computer Supported Cooperative Work in Design (CSCWD)

作者： Yuan, Zhongda Ma, Yuchun Bian, Jinian Zhao, Kang Tsinghua Univ Dept Comp Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781467360852;9781467360845

Control and data flow Graph (CDFG) is a universal description of program behavior, which is widely used in the co-design of software and hardware. The derivation of CDFG has been done mostly by manually or automatically analyzing corresponding source code, which makes this process time-consuming, error-prone and incomplete. In this paper, we proposed an automated design flow based on runtime instrumentation to generate Enhanced CDFG (ECDFG) with additional runtime information. Though the approach of runtime instrumentation is widely used in software debugging to analyze the program with the accurate runtime information, it is rarely used in software and hardware co-design due to the huge trace data and processing overhead. To overcome the bottle neck of the runtime instrumentation approach, Parallel Background Event Logger is proposed to compress and save the huge amount of trace data. Hierarchical loop structures are detected by intersecting reachable set and backward reachable set. Precise data dependency information is deducted by an address based analytical method named Shower Line Algorithm. With these algorithms and techniques, a set of automatic design tools are implemented to collect runtime events, identify nested and implicit loops and deduct data dependance between modules. Exemplar results demonstrated that Enhanced CDFGs for various programs can be generated correctly with acceptable overhead.

关键词： data flow graphs hardware-software codesign instrumentation parallel processing program control structures program debugging source coding

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An ameliorated methodology for the abstraction of usecases from software requirements specification

An ameliorated methodology for the abstraction of usecases f...

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2013 Science and Information Conference, SAI 2013

作者： Handigund, Shivanand M. Shivaram, A.M. Comp Sc. and Engg. Bangalore Institute of Technology Bangalore 560 004 India Dept of MCA Bangalore Institute of Technology Bangalore 560 004 India

ISBN: (纸本)9780989319300

Information systems of business process are realized through software projects which use the specific software requirements specification (SRS) provided for them as the base. The SRS contains details of the information system through which appropriate software can be developed. The information systems are also viewed prospectively with different equiponderant pragmatics like work, work process or usecase. The usecase is one of the prime perspective views each of whose sum forms the information system. In this paper, an attempt is made to abstract usecases statements of all actors from unformatted unstructured SRS text. The stages involve moulding the SRS, creating control flow & data flow graphs, creating appropriate slicing criteria, creating actor & actors' interface attributes table, create slicing criteria for each usecase and then slice the relevant statements for each usecase. Here we have attempted to use Weiser modified algorithm [1] to abstract exact usecase from first cut usecase. The slicing criterion is obtained through the intersection of actor's interface attributes and the referenced / defined attributes present between two consecutive actors (first cut usecase). Attempts have been made to resolve synonyms & heteronyms present in the SRS. The correctness & completeness of the proposed methodology depends on the realization of actor & actors' interface attributes. © 2013 The Science and Information Organization.

关键词： data flow graphs

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Using data-flow analysis in MAS for power-aware HPC runs

Using data-flow analysis in MAS for power-aware HPC runs

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2013 11th International Conference on High Performance Computing and Simulation, HPCS 2013

作者： Varrette, Sebastien Danoy, Gregoire Guzek, Mateusz Bouvry, Pascal Research Unit University of Luxembourg 16 rue Richard Coudenhove-Kalergi L-1359 Luxembourg Luxembourg University of Luxembourg 16 rue Richard Coudenhove-Kalergi L-1359 Luxembourg Luxembourg

""With a growing concern on the considerable energy consumed by HPC platforms and data centers, research efforts are targeting toward green approaches with higher energy efficiency. Hence, the use of low pow... 详细信息

ISBN: (纸本)9781479908363

关键词： computer centres data flow analysis data flow graphs directed graphs green computing multi-agent systems parallel programming power aware computing scheduling

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Comparison of configurations of data path architecture developed using template

Comparison of configurations of data path architecture devel...

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International Conference on Advances in Computing, ICAdC 2012

作者： Bala Tripura Sundari, B. Krishnan, Varsha Amrita Vishwa Vidyapeetham Coimbatore 641112 India

ISBN: (纸本)9788132207399

data path circuits play a vital role in today's processors. data path, which defines the structural model for interconnection of resources, needs to be flexible. It consists of a computing architecture modeled by a set of virtual templates. The focus of this work is to obtain the efficient configuration of the templates in order to map data intensive applications. The resource constrained scheduling process is employed to schedule the operations pertaining to different configurations. To achieve this scheduling, the data flow graph is modeled by grouping the resources for different configurations as a vertex cover model. data intensive applications involve large amounts of data reuse and the number of registers and ports required is determined for each configuration. The number of registers, ports and latency are measures of efficiency of the configuration and using these measures the most efficient configuration of the templates to map an application is determined. © 2013 Springer.

关键词： data flow graphs

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Composing and executing parallel data-flow graphs with shell pipes

Composing and executing parallel data-flow graphs with shell...

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4th Workshop on Workflows in Support of Large-Scale Science, WORKS '09, in Conjunction with SC 2009

作者： Walker, Edward Xu, Weijia Chandar, Vinoth Texas Advanced Computing Center University of Texas at Austin Austin TX United States Oracle Corporation 400 Oracle Parkway Redwood Shores CA United States

ISBN: (纸本)9781605587172

In this paper we extend the concept of shell pipes to incorporate forks, joins, cycles, and key-value aggregation. These extensions enable the implementation of a class of data-flow computation with strong deterministic properties, and provide a simple yet powerful coordination layer for leveraging multi-language and legacy components for large-scale parallel computation. Concretely, this paper describes the design and implementation of the language extensions in Bourne Again SHell (BASH), and examines the performance of the system using micro and macro benchmarks. The implemented system is shown to scale to thousands of processors, enabling high throughput performance for millions of processing tasks on large commodity compute clusters. Copyright 2009 ACM.

关键词： data flow graphs

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FIR filter design based on retiming & automation using VLSI design metrics

FIR filter design based on retiming & automation using VLSI ...

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2013 International Conference on Technology, Informatics, Management, Engineering and Environment, TIME-E 2013

作者： Yagain, Deepa Vijaya, Krishna A. People's Education Society Institute of Technology Bangalore-560 085 Karnataka India

ISBN: (纸本)9781467357326

Finite Impulse Response (FIR) Filter can be designed by formulation of specifications which are for a particular application requirement. In this paper, an efficient FIR filter is designed using register minimization retiming technique. Also, an optimization environment is designed such that filter components of post retimed circuit such as adder and multiplier are upgraded depending on the VLSI design metrics such as area, speed or power as according to designer's need and synthesizable code in Hardware Description Language [HDL] is generated. Retiming is a technique in which alteration to the critical path of FIR filter is done by changing the placement of the registers in the original FIR filter circuit. The placement of registers has to be made such that the functionality is not altered and critical path is minimized. The critical path minimization reduces overall clock period thereby increasing the clock frequency in retiming. At times, this may lead to increased register counts. The register minimization retiming provides the best compromise of clock period and register count. The FIR filter which needs to be optimized can be given to the optimization environment either as data flow graph or as a matrix. The designed optimization environment performs register minimization retiming and generates the synthesizable HDL of filter circuit. Also, different adders and multipliers are designed and their VLSI design metrics are compared in this work. Based on this comparison, adder and multiplier for a particular performance parameter such as area, power or delay is identified. A GUI is designed with Nokia QT for binding retimed FIR filter with efficient adder and multiplier components. Hence using register minimization retiming and component binding based on VLSI design metrics, an optimized digital FIR filters can be designed with minimum design cycle time. © 2013 IEEE.

关键词： data flow graphs

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Capturing and Mitigating the NBTI Effect During the Design flow for Extensible Processors

Capturing and Mitigating the NBTI Effect During the Design F...

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International Conference on Design & Technology of Integrated Systems in Nanoscale Era

作者： Mehdi Kamal Ali Afzali-Kusha Saeed Safari Massoud Pedram Behzad Eghbalkhah School of Electrical and Computer Engineering University of Tehran Iran Electrical Engineering Department University of Southern California USA

ISBN: (纸本)9781467360395

This paper studies the impact of the delay degradation arising from the Negative Bias Temperature Instability (NTBI) effect on the extended instruction set architecture (ISA) and the ALU design of extensible processors. In particular, the NBTI delay degradation on the performance of extensible processors is modeled during the conventional design flow. While the results of this study show that, in some cases, the lifetime of the extensible processors is decreased, in most cases, the extended ISA is able to improve the lifetime compared to the baseline processor. Next, three different design flows are presented to lower the NBTI effect. These flows are based on reducing the stress on custom instructions (CIs) by considering the number of occurrences of the selected CIs in the data flow graph of the target application and by pruning the CIs whose NBTI-induced delay degradations are large and result in slow down of the extensible processor. Experimental results assess the effectiveness of the proposed methods.

关键词： Effect During Design Design flow Negative bias temperature instability EXPANDABLE PROCESSOR 4-nitrobenzylthioinosine data flow graphs cis

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Minimization of I/O delay in the architectural synthesis of DSP data flow graphs

Minimization of I/O delay in the architectural synthesis of ...

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IEEE International Symposium on Circuits and Systems

作者： Itradat, Awni Ahmad, M. O. Shatnawi, Ali Concordia Univ Dept Elect & Comp Engn Montreal PQ H3G 1M8 Canada Jordan Univ Sci & Technol Dept Comp Engn Irbid Jordan

ISBN: (纸本)9781424420780

This paper presents a new technique for the minimization of I/O delay in the architectural synthesis of cyclic data flow graphs (DFG) representing DSP algorithms taking into consideration the inter-processor communication delays. In this paper, the question of optimizing the I/O delay without scarifying the iteration period (throughput) with non-negligible inter-processor communication overhead is addressed. The proposed technique operating on the cyclic DFG of a DSP algorithm is designed to evaluate the relative firing times of the nodes by using Floyd-Warshall's longest path algorithm so that the inter-processor communication overhead is taken into consideration to provide an optimized time and processor schedule. Moreover, the proposed scheme is applied to well-know DSP benchmarks and seen that it is efficient in minimizing the I/O delay without scarifying the iteration period.

关键词： data flow graphs

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Verification of Parameterized Concurrent Programs By Modular Reasoning about data and Control 12

Verification of Parameterized Concurrent Programs By Modular...

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39th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages

作者： Farzan, Azadeh Kincaid, Zachary Univ Toronto Toronto ON M5S 1A1 Canada

ISBN: (纸本)9781450310833

In this paper, we consider the problem of verifying thread-state properties of multithreaded programs in which the number of active threads cannot be statically bounded. Our approach is based on decomposing the task into two modules, where one reasons about data and the other reasons about control. The data module computes thread-state invariants (e. g., linear constraints over global variables and local variables of one thread) using the thread interference information computed by the control module. The control module computes a representation of thread interference, as an incrementally constructed data flow graph, using the data invariants provided by the data module. These invariants are used to rule out patterns of thread interference that can not occur in a real program execution. The two modules are incorporated into a feedback loop, so that the abstractions of data and interference are iteratively coarsened as the algorithm progresses (that is, they become weaker) until a fixed point is reached. Our approach is sound and terminating, and applicable to programs with infinite state (e. g., unbounded integers) and unboundedly many threads. The verification method presented in this paper has been implemented into a tool, called DUET. We demonstrate the effectiveness of our technique by verifying properties of a selection of Linux device drivers using DUET, and also compare DUET with previous work on verification of parameterized Boolean program using the Boolean abstractions of these drivers.

关键词： Verification Algorithms Reliability Concurrency Abstract Interpretation Compositional Reasoning data flow graphs Parameterized Programs Thread Invariants

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A cycle-level parallel simulation technique exploiting both space and time parallelism

A cycle-level parallel simulation technique exploiting both ...

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23rd IEEE International Symposium on Rapid System Prototyping, RSP 2012

作者： Yun, Dukyoung Yi, Youngmin Kim, Sungchan Ha, Soonhoi Samsung Electronics Korea Republic of University of Seoul Korea Republic of Chonbuk National University Korea Republic of Seoul National University Korea Republic of

ISBN: (纸本)9781467327862

As the number of processors increases in an MPSoC, the simulation performance degrades significantly if all component simulators run sequentially. Recently a novel parallel simulation technique was proposed to exploit spaceparallelism by distributing component simulators to multiple host cores. In this paper, we boost the performance further by exploiting time-parallelism in case that an application is specified as a task graph following the data-flow semantics, such as a KPN (Kahn Process Network) or a data flow graph. Time-parallel simulation enables parallel execution of tasks in different intervals in the timeline by resolving data dependencies between them with redundant host code execution. The proposed technique provides higher degree of parallelism beyond the number of processors in the target architecture. Experiments with real-life multimedia examples prove the effectiveness of the proposed approach. ©2012 IEEE.

关键词： data flow graphs

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