检索结果-内蒙古大学图书馆

33rd IEEE Real-Time Systems Symposium

作者： Betts, Adam Univ London Imperial Coll Sci Technol & Med Dept Comp London SW7 2AZ England

ISBN: (纸本)9780769548692;9781467330985

Implicit Path Enumeration (IPE) is the most popular calculation technique used in WCET analysis as it generally provides the most precision. It utilises the Control flow Graph (CFG) to build a constraint system consisting of, amongst others, structural constraints (derived from the CFG) and relative capacity constraints (loop bounds relative to the innermost enclosing loop). However, solving the constraint system is an NP-hard problem and reducing the size of the model is therefore desirable. This paper shows that, when the CFG loops are free of break-like constructs, the constraint system produced by IPE consists of many superfluous structural constraints in that their elimination does not detract from the precision of the WCET estimate. We demonstrate this fact by building an alternative constraint system from a new intermediate data structure called the Super Block Control flow Graph (SB-CFG). Furthermore, we illustrate how the SB-CFG allows us to deduce when relative capacity constraints are actually needed - until now they have been considered mandatory to avoid overestimations with loops. Comparing the two constraint systems across a large number of automatically generated control flow graphs, our results show there is: a 50% reduction in the number of variables;a 55% reduction in the number of constraints;and a 69% reduction in solving time.

关键词： computational complexity constraint handling data flow analysis data flow graphs data structures

来源：评论

学校读者我要写书评

暂无评论

FPGA Based Path Solvers for DFGs in High Level Synthesis

FPGA Based Path Solvers for DFGs in High Level Synthesis

引用

2nd International Conference on Advances in Computational Tools for Engineering Applications (ACTEA)

作者： Yagain, Deepa Vijayakrishna, A. Nikhil, P. Adarsh, A. Karthikeyan, S. PESIT Dept ECE Bangalore Karnataka India

ISBN: (纸本)9781467324892

Retiming is a transformation which can be applied to Digital Signal Processing Blocks that can increase the clock frequency. Folding in retiming can also reduce the resource utilization and power consumption. This transformation requires computation of critical path and shortest path at various stages. In this particular work, a FPGA based path finder is designed to compute critical path and shortest path in the data flow graphs (DFGs). Since this path computation is performed using FPGA based IC, the speed of retiming transformation increases. This also reduces the resource utilization of the general purpose machine in which retiming transformation is usually performed. Critical path in sequential circuit is defined as the longest path between any two storage components. This determines the minimum feasible clock period for any sequential circuit. We need to compute the critical path before we apply retiming transformation to any digital Signal Processing block. Similarly shortest path computation is required in retiming while solving the system inequalities in the constraint graph. In this work, shortest path computation is performed using Floyd-Warshall algorithm. Since FPGA based hardware for path solvers performs much faster when compared to general purpose processor [where actual retiming is done], the speed with which the retiming transformation is performed increases. Xilinx ISE design suit is used with device as SPARTEN3E XC3S250E for the work presented.

关键词： Critical Path Floyd-Warshall algorithm Hardware Description Language (HDL) data flow graphs retiming System inequality Clock frequency

来源：评论

学校读者我要写书评

暂无评论

Model Based Testing using an Extended Context Free Grammar

Model Based Testing using an Extended Context Free Grammar

引用

IEEE International Conference on Industrial Technology (ICIT)

作者： Mahesh, M. Murthy, P. V. R. Siemens Corp Res Technol Alpharetta GA USA

ISBN: (纸本)9781467303422

There exists a frequent requirement to test components or modules that accept various parameters which need to be combined in specific ways, as dictated by constraints specified in a natural language. Extended Context Free Grammars (ECFG) are suitable for modeling the above test requirements. A tool is built that accepts a test design in the form of an ECFG and generates test data or scripts automatically. With the objective of providing a user-friendly interface for expressing test designs in ECFG, a visual formalism using data-flow graphs is provided by the tool. Some case studies are reported to demonstrate the benefits of the approach.

关键词： Design for testability context-free grammars data flow graphs observational data test assembly flowcharts TESTING REQUIREMENTS

来源：评论

学校读者我要写书评

暂无评论

Parametric Throughput Analysis of Synchronous data flow graphs 08

Parametric Throughput Analysis of Synchronous Data Flow Grap...

引用

2008 Design, Automation and Test in Europe (DATE 2008), vol.1

作者： A. H. Ghamarian M. C. W. Geilen T. Basten S. Stuijk Eindhoven University of Technology

ISBN: (纸本)9783981080131

Synchronous data flow graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiprocessor platforms. One of the most prominent performance constraints of concurrent real-time applications is throughput. For given actor execution times, throughput can be verified by analyzing the SDFG models of such applications, for instance using maximum cycle mean analysis or state space analysis. In various contexts, such as design space exploration or run-time reconfiguration, many fast throughput computations are required for varying actor execution times. We present methods to compute throughput of an SDFG where actor execution times can be parameters. The throughput of these graphs is obtained in the form of a function of these parameters. Recalculation of throughput is then merely an evaluation of this Junction for specific parameter values, which is much faster than the standard throughput analysis. We propose three different algorithms for parametric throughput analysis and evaluate these algorithms experimentally, showing the feasibility of the approach and showing that a divide and conquer algorithm performs best.

关键词： Throughput data flow graphs actor MULTIMEDIA APPLICATION Space Exploration Junction Device Component Crossing state space Legal Executions

来源：评论

学校读者我要写书评

暂无评论

Design optimization platform for synthesizable high speed digital filters using retiming technique

Design optimization platform for synthesizable high speed di...

引用

2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012

作者： Yagain, Deepa Vijaya Krishna, A. Chennapnoor, Sheetal People's Education Society Institute of Technology Bangalore-560 085 Karnataka India

ISBN: (纸本)9781467323963

In signal processing applications the time critical sections are iterative and recursive and requires various optimization techniques for performance enhancement. Most of these applications require each iteration to be executed under a specific time constraint associated with the data input rate. Using optimization techniques like retiming, we achieve the desired performance. Digital filters are the most common blocks in signal processing applications and they can be represented by synchronous data-flow graphs (DFGs). Applying retiming techniques on the synchronous data flow graphs results in obtaining high speed digital circuits. Retiming is the process of rearranging the storage elements in the circuit to reduce the cycle time without changing its functionality. In this paper, a single optimization environment is developed for retiming the DSP filter blocks using cutset and clock period minimization techniques. Cutset retiming is specially used for filters designed for single processor systems. An optimized digital filter circuit is obtained after retiming from design optimization environment. Also, the HDL(Hardware Description Language) code of the optimized filter circuit is automatically generated and microarchitectural optimizations like usage of parallel prefix tree adders, supply voltage scaling are done at structural level of the circuit which still enhances the filter design performance. © 2012 IEEE.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

A three-dimensional integrated accelerator

A three-dimensional integrated accelerator

引用

15th Euromicro Conference on Digital System Design, DSD 2012

作者： Mehdipour, Farhad Nunna, Krishna C. Inoue, Koji Murakami, Kazuaki J. E-JUST Center Kyushu University Japan Department of Advanced Informatics Kyushu University Japan

ISBN: (纸本)9780769547985

We propose a three-dimensional (3D) reconfigurable data-path accelerator which is capable of running partitioned large data flow graphs (DFGs) on the layers of 3D stack, while inter-layer connections are implemented by means of through-silicon vias (TSVs). A tool for mapping data flow graphs has been developed, and a key 3D-specific problem namely routing nets on 3D architecture has been discussed in details as well. Conducted experiments demonstrate smaller footprint area and higher performance for the 3D accelerator comparing with 2D counterpart. © 2012 IEEE.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Object-oriented approach to rapid custom instruction design

Object-oriented approach to rapid custom instruction design

引用

2012 IEEE Faible Tension Faible Consommation, FTFC 2012

作者： Kallel, Emna Aoudni, Yassine Abid, Mohamed CES Laboratory Univ. Sfax ENIS School BP 1173 Sfax 3038 Tunisia

ISBN: (纸本)9781467308205

Due to continuous evolution of Systems-on-Chip (SoC), the complexity of their design and development has augmented exponentially. To deal with the ever-growing complexity of such embedded systems, we introduce, in this paper, an object-oriented approach to rapid SoC design using auto-generation of hardware custom instructions to simplify and accelerate the SoC design process. In our approach, a data flow Graph (DFG) is adopted as a representation of the arithmetic operation to convert it to a custom instruction. Then VHDL code will be automatically generated. The input C code is automatically updated for calling the new hardware components. To prove the effectiveness of the proposed approach, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application validate our approach and demonstrate how the proposed framework facilitates and accelerates the SoC design process at low costs. © 2012 IEEE.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Dfg based optimization for AES implementation

引用

ICIC Express Letters 2012年第6期6卷 1417-1422页

作者： Li, Yibin Chen, Renhai Jia, Zhiping Xie, Shuai Department of Computer Science and Technology Shandong University No. 1500 Shunhua Rd. High-Tech Zone Jinan 250100 China

The Advanced Encryption Standard (AES) is a symmetric-key encryption standard adopted by the U.S. government. It is widely used in data transmission. In many applications, a specific accelerator is in demand to facilitate higher throughput with less memory utilization. In this paper, the specific instructions for AES are initially identified by using custom simulator, and then further optimizations take place using data flow Graph (DFG). In implementation aspect, Electronic System Level (ESL) method has been adopted. Finally, it has shown 60% performance improvement with less space complexity compared with ARM instruction. © 2012 ICIC International.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

A template based task mapping framework for coarse grain reconfigurable multimedia processor

引用

Journal of Computational Information Systems 2012年第1期8卷 159-167页

作者： Sheng, Weiguang He, Weifeng Mao, Zhigang School of Microelectronics Shanghai Jiao Tong University Shanghai 200240 China

A novel task mapping framework based on template technique is developed for efficiently mapping multimedia applications to the REmusII coarse reconfigurable processor. Task mapping transforms computation intensive codes written in high level language to configurations running on reconfigurable processor and hence be critical for the usability, flexibility and speedup of the coarse reconfigurable processor. In this paper, computational intensive blocks of the application codes are modeled as DFGs (data flow graphs), and the corresponding configurations are generated automatically or manually aforehand based on the DFGs. The DFGs and associated configurations, auxiliary data are regarded as a functional unit called template, while the succeeded scheduling and mapping tasks are carried out at the template granularity. The templates are organized and stored in a library powered by an open source relational database-Berkely DB. Task mapping can be done by retrieving corresponding configurations from the template library, filling out supplemental information and sending to the reconfigurable processor to execute through dedicated interfaces. We developed an elementary prototype for the template based task mapping and various useful templates have been generated using the proposed method. Experiments carried out on the REmusII coarse reconfigurable processor show that the speedup gain can be up to 100X, proved that the proposed technique is suitable for mapping computational intensive applications to coarse reconfigurable processors with complex structure. © 2012 Binary Information Press January 2012.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Mixing static and dynamic strategies for high performance and low area reconfigurable systems

引用

International Journal of High Performance Systems Architecture 2012年第1期4卷 13-24页

作者： Rutzig, Mateus Beck Beck, Antonio Carlos Schneider Computer Science Program Informatics Institute Federal University of Rio Grande Do sul Bento Gonçalves 9500 - Setor IV Porto Alegre Brazil

Reconfigurable architectures can be seen as a possible solution to increase performance of current embedded systems. While dynamic reconfigurable systems present different degrees of adaptability at the price of huge area overhead, static exploitation tools can be used at design time to generate a tailored reconfigurable unit with small area requirements. However, the speedup using static tools will be limited only to the specific application set previously analysed. Therefore, we propose a technique that presents the best compromise between both approaches. After a high performance and low-power reconfigurable unit, optimised in area, is produced by a static exploitation tool, it is coupled to a dynamic hardware mechanism responsible for accelerating applications not foreseen at design time. Hence, both the capability of adaptation and the binary compatibility are maintained. We are able to save up to 40% in area and 77% in power, without significant losses in performance or adaptability. Copyright © 2012 Inderscience Enterprises Ltd.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：