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8th International Conference on Parallel Processing and Applied Mathematics

作者： Smyk, Adam Tudruj, Marek Polish Japanese Inst Informat Technol PL-02008 Warsaw Poland

ISBN: (纸本)9783642143892

This paper presents a methodology, which enables an optimized execution of FDTD (Finite Difference Time Domain) computations in a streaming model architecture (Cell BE processors). A data flow graph that represents the FDTD computations in an irregular wave propagation area is transformed into a set of tiles. Each tile represents regular computations for a small part of a given computational area. Tiles are injected into computational nodes and processed in a pipe-like manner. It will be shown that such approach enables solving the FDTD problem with a speedup almost equal to the ideal one. Several computation optimization methods are presented. Efficiency of streaming computations for various simulation parameters is discussed. Experimental results obtained for the streaming model on a physical PS3 machine are presented as well.

关键词： data flow graphs

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Automatic Test Case Selection and Generation for Regression Testing of Composite Service Based on Extensible BPEL flow Graph

Automatic Test Case Selection and Generation for Regression ...

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International Conference on Software Maintenance

作者： Li, Bixin Qiu, Dong Ji, Shunhui Wang, Di Southeast Univ Sch Engn & Comp Sci Nanjing 210096 Peoples R China

ISBN: (纸本)9781424486298

Services are highly reusable, flexible and loosely coupled, which makes the evolution and the maintenance of composite services more complex. Evolution of BPEL composite service covers changes of processes, bindings and interfaces. In this paper, an approach is proposed to select and generate test cases during the evolution of BPEL composite service. The approach identifies the changes by using control-flow analysis technique and comparing the paths in new composite service version and the old one using extensible BPEL flow graph (or XBFG). Message flow is appended to the control flow so that XBFG can describe the behavior of composite service integrally. The binding and predicate constraint information added in XBFG elements can be used in path selection and test case generation. Theory analysis and case study both show that the approach is effective, and test cases coverage rate is high for the changes of processes, bindings and interfaces.

关键词： BPEL composite service Web service Web services XBFG element automatic test case generation automatic test case selection automatic test pattern generation business data processing composite service evolution composite service maintenance control-flow analysis data flow analysis data flow graphs extensible BPEL flow graph message flow path selection program testing regression testing software maintenance

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ESTIMATING TEST COST DURING data PATH AND CONTROLLER SYNTHESIS WITH LOW POWER OVERHEAD

ESTIMATING TEST COST DURING DATA PATH AND CONTROLLER SYNTHES...

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23rd Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Harmanani, Haidar M. Kodeih, Maya Lebanese Amer Univ Dept Comp Sci & Math Byblos 14012010 Lebanon

This paper presents a method for concurrent BIST cost estimation during testable data path allocation. The method integrates testability in the design process and generates a distributed test controller that aims to m... 详细信息

ISBN: (纸本)9781424453771

关键词： circuit testing concurrent BIST cost estimation control engineering computing control system synthesis controller synthesis costing data flow graphs data path synthesis distributed test controller high level synthesis low power overhead

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Multi-CMP Module System Based on a Look-Ahead Configured Global Network

Multi-CMP Module System Based on a Look-Ahead Configured Glo...

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8th International Conference on Parallel Processing and Applied Mathematics

作者： Laskowski, Eryk Masko, Lukasz Tudruji, Marek Inst Comp Sci PAS PL-01237 Warsaw Poland

ISBN: (纸本)9783642143892

The impressive progress of Systems on Chip (SoC) design enables a revival of efficient massively parallel systems based on many Chip Multiprocessor (CM P) modules interconnected by global networks. The paper presents methods for the optimized program execution control for such modular CMP systems. At the CMP module level, communication through shared memory is applied, improved by a novel efficient group communication mechanism (reads on, the fly). The inter module global communication is implemented as a message passing between module memories placed in a shared address space. A two-phase structuring algorithm is described for programs represented as macro data-flow graphs. In the first phase, program tasks inside the CMP modules are scheduled, using an algorithm based on the notion of moldable tasks. In the next phase, the moldable task graph is structured for optimized communication execution in the global interconnection network according to the look-ahead link connection setting paradigm. Simulation experiments evaluate the efficiency and other properties of the proposed architectural solutions.

关键词： data flow graphs

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Retiming Arithmetic datapaths using Timed Taylor Expansion Diagrams

Retiming Arithmetic Datapaths using Timed Taylor Expansion D...

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15th IEEE International High Level Design Validation and Test Workshop (HLDVT)

作者： Gomez-Prado, Daniel Kim, Dusung Ciesielski, Maciej Boutillon, Emmanuel Univ Massachusetts Amherst Amherst MA 01003 USA Univ Bretagne Sud Lab STICC Lorient France

ISBN: (纸本)9781424478064

This paper describes an extension to the Taylor Expansion Diagrams (TED), called Timed TEDs, which makes it possible to represent sequential arithmetic datapaths. Timed TEDs enable register and clock period minimization while performing factorizations and common sub expression eliminations in the data flow graph (DFG). Specifically, timed TEDs allow a wider range of retiming options as the computations in the DFG can be modified while performing retiming. In this paper we discuss the formalism of timed TEDs and the restrictions it imposes on the TED variable ordering.

关键词： data flow graphs

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The construction and management of template library for coarse-grained reconfigurable system

The construction and management of template library for coar...

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2010 International Conference on Computer Application and System Modeling, ICCASM 2010

作者： Cui, Xiao Sheng, Weiguang Wang, Qin School of Microelectronics Shanghai Jiaotong University Shanghai China

ISBN: (纸本)9781424472369

Template-based task partitioning and scheduling can dramatically improve the scheduling efficiency and resource utilization in the coarse-grained reconfigurable system. However, when the number of templates is large, the effective organization and management of the templates is a hard problem. Here a template library based method is employed to address the above problem. Various templates are organized and managed within the database;an improved canonical labeling algorithm for DFG (data flow graph) is provided to speed up the template insertion and query by avoiding numerous graph isomorphism operations;an automatic tool is also designed and implemented for the template execution on the RCA (reconfigurable cell array), including the effective methods for context words generation, storage and matching. Experiments are carried out and the results show that the provided method can effectively organize and manage the templates. Moreover, the experiments also indicate that the methods can speed up the template insertion and query operations dramatically.

关键词： data flow graphs

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A globally-interconnected modular CMP system with communication on the fly

A globally-interconnected modular CMP system with communicat...

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IEEE International SOC Conference

作者： Tudruj, Marek Masko, Lukasz Institute of Computer Science Polish Academy of Sciences ul. Ordona 21 01-237 Warsaw Poland Polish-Japanese Institute of Information Technology ul. Koszykowa 86 02-008 Warsaw Poland

ISBN: (纸本)9781424466832

The paper presents new methods for data communication for modular CMP systems interconnected by a global network. A special group communication called communication on the fly is applied between processor core data caches. It is based on data reads on the fly on data busses connecting L1 and L2 data caches. Similar data communication is applied for global network. Programs are built following macro data flow graphs. Simulation experiments evaluate the proposed solutions. © 2010 IEEE.

关键词： data flow graphs

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Throughput analysis of synchronous data flow graphs

Throughput analysis of synchronous data flow graphs

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6th International Conference on Application of Concurrency to System Design, ACSD 2006

作者： Ghamarian, A.H. Geilen, M.C.W. Stuijk, S. Basten, T. Moonen, A.J.M. Bekooij, M.J.G. Theelen, B.D. Mousavi, M.R. Eindhoven University of Technology Philips Research Laboratories Eindhoven

ISBN: (纸本)0769525563

Synchronous data flow graphs (SDFGs) are a useful tool for modeling and analyzing embedded data flow applications, both in a single processor and a multiprocessing context or for application mapping on platforms. Throughput analysis of these SDFGs is an important step for verifying throughput requirements of concurrent real-time applications, for instance within design-space exploration activities. Analysis of SDFGs can be hard, since the worst-case complexity of analysis algorithms is often high. This is also true for throughput analysis. In particular, many algorithms involve a conversion to another kind of data flow graph, the size of which can be exponentially larger than the size of the original graph. In this paper, we present a method for throughput analysis of SDFGs, based on explicit state-space exploration and we show that the method, despite its worst-case complexity, works well in practice, while existing methods often fail. We demonstrate this by comparing the method with state-of-the-art cycle mean computation algorithms. Moreover, since the state-space exploration method is essentially the same as simulation of the graph, the results of this paper can be easily obtained as a byproduct in existing simulation tools. © 2006 IEEE.

关键词： data flow graphs

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Towards co-design of HW/SW/Analog systems

Lecture Notes in Electrical Engineering

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Lecture Notes in Electrical Engineering 2010年 78卷 1-24页

作者： Grimm, Christoph Damm, Markus Haase, Jan Department of Embedded Systems Vienna University of Technology Gusshausstrae 27-29 1040 Wien Austria

ISBN: (纸本)9783642167669

We give an overview of methods for modeling and system level design of mixed HW/SW/Analog systems. For abstract, functional modeling we combine Kahn Process Networks and Timed data flow graphs. In order to model concrete architectures, we combine KPN and TDF with transaction level modeling. We describe properties and issues raised by the combination of these models and show how these models can be used for executable specification and architecture exploration. For application in industrial practice we show how these models and methods can be implemented by combining the standardized SystemC AMS and TLM extensions. © 2010 Springer-Verlag Berlin Heidelberg.

关键词： data flow graphs

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Time-multiplexed data flow Graph for the Design of Configurable Multiplier Block

Time-multiplexed Data Flow Graph for the Design of Configura...

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IEEE International Symposium on Circuits and Systems (ISCAS 2009)

作者： Chen, Jiajia Chang, Chip-Hong Jong, Ching-Chuen Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore Singapore Nanyang Technol Univ Ctr Integrated Circuits & Syst Singapore Singapore

ISBN: (纸本)9781424438273

This paper proposes a new design methodology to reduce the logic complexity of reconfigurable multiplier block (ReMB). The minimization problem is modeled as a scheduled time-multiplexed data flow graph (TDFG). To reduce the number of operators to be scheduled in the DFG, the most dominant common subexpressions are greedily identified and eliminated based on the subexpressions' frequencies which are updated dynamically in the optimization process. High level synthesis algorithm is then employed to perform the scheduling of operators to control steps. By binding the compatible operators in the same control steps, more operators can be saved. Two design examples are used to demonstrate the effectiveness of the proposed algorithm. On average, the logic complexity of the proposed ReMB design is about 19% lower than that of the classical ReMB methods, and 7% lower than that of the latest and most competitive ReMB design methodology.

关键词： data flow graphs

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