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13th USENIX Symposium on Operating Systems Design and Implementation, OSDI 2018

作者： Gjengset, Jon Schwarzkopf, Malte Behrens, Jonathan Araújo, Lara Timbó Ek, Martin Kohler, Eddie Frans Kaashoek, M. Morris, Robert MIT CSAIL Norwegian University of Science and Technology Norway Harvard University United States

ISBN: (纸本)9781939133083

We introduce partially-stateful data-flow, a new streaming data-flow model that supports eviction and reconstruction of data-flow state on demand. By avoiding state explosion and supporting live changes to the data-flow graph, this model makes data-flow viable for building long-lived, low-latency applications, such as web applications. Our implementation, Noria, simplifies the backend infrastructure for read-heavy web applications while improving their performance. A Noria application supplies a relational schema and a set of parameterized queries, which Noria compiles into a data-flow program that pre-computes results for reads and incrementally applies writes. Noria makes it easy to write high-performance applications without manual performance tuning or complex-to-maintain caching layers. Partial statefulness helps Noria limit its in-memory state without prior data-flow systems' restriction to windowed state, and helps Noria adapt its data-flow to schema and query changes while on-line. Unlike prior data-flow systems, Noria also shares state and computation across related queries, eliminating duplicate work. On a real web application's queries, our prototype scales to 5× higher load than a hand-optimized MySQL baseline. Noria also outperforms a typical MySQL/memcached stack and the materialized views of a commercial database. It scales to tens of millions of reads and millions of writes per second over multiple servers, outperforming a state-of-the-art streaming data-flow system. © Proceedings of NSDI 2010: 7th USENIX Symposium on Networked Systems Design and Implementation. All rights reserved.

关键词： data flow graphs

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A flexible runtime system for image processing in a distributed computational environment for an unmanned aerial vehicle

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INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE 2006年第5期20卷 763-780页

作者： Nordberg, Klas Doherty, Patrick Forssen, Per-Erik Wiklund, Johan Andersson, Per Linkoping Univ Dept Elect Engn Comp Vis Lab S-58183 Linkoping Sweden Linkoping Univ Dept Comp Sci Knowledge Proc Lab S-58183 Linkoping Sweden Lund Univ Dept Comp Sci S-22100 Lund Sweden

A runtime system for implementation of image processing operations is presented. It is designed for working in a flexible and distributed environment related to the software architecture of a newly developed UAV system. The software architecture can be characterized at a coarse scale as a layered system, with a deliberative layer at the top, a reactive layer in the middle, and a processing layer at the bottom. At a finer scale each of the three levels is decomposed into sets of modules which communicate using CORBA, allowing system development and deployment on the UAV to be made in a highly flexible way. Image processing takes place in a dedicated module located in the process layer, and is the main focus of the paper. This module has been designed as a runtime system for data flow graphs, allowing various processing operations to be created online and on demand by the higher levels of the system. The runtime system is implemented in Java, which allows development and deployment to be made on a wide range of hardware/software configurations. Optimizations for particular hardware platforms have been made using Java's native interface.

关键词： image processing autonomous systems reconfigurability runtime system for image processing data flow graphs unmanned aerial vehicles

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Memory optimal single appearance schedule with dynamic loop count for synchronous dataflow graphs 06

Memory optimal single appearance schedule with dynamic loop ...

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11th Asia and South Pacific Design Automation Conference

作者： Oh, Hyunok Dutt, Nikil Ha, Soonhoi Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA Seoul Natl Univ Sch EECS Seoul South Korea

ISBN: (纸本)0780394518

In this paper, we propose a new single appearance schedule for synchronous dataflow programs to minimize data memory and code memory size simultaneously. While a single appearance schedule promises only one appearance of each node definition in the generated code, it requires significant amount of data memory overhead compared with a buffer optimal schedule allowing multiple appearance. The key idea of the proposed technique is to make a dynamic decision of loop count to make a schedule quasi-static. The proposed quasi-static schedule produces a single appearance schedule code with minimum data memory requirement. We prove that every buffer optimal schedule can be transformed to our single appearance schedule which requires optimal buffer size for arbitrary synchronous dataflow graphs. The only penalty for the proposed technique is slight performance overhead of computing loop counts dynamically. In order to minimize the overhead we propose optimization techniques. Experimental results show that the proposed algorithm reduces 20% total memory with less than 1% performance overhead compared with the previous single appearance schedule algorithms.

关键词： data flow graphs processor scheduling storage management code memory dynamic decision dynamic loop count loop counts memory optimal single appearance schedule minimum data memory schedule code schedule quasi-static synchronous dataflow graph

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Parallel FDTD computations optimized by program macro data flow graph redeployment

Parallel FDTD computations optimized by program macro data f...

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International Symposium on Parallel Computing in Electrical Engineering

作者： Smyk, Adam Tudruj, Marek Polish Japanese Inst Informat Technol 86 Koszykowa Str PL-02008 Warsaw Poland Polish Acad Sci Inst Comp Sci PL-01237 Warsaw Poland

ISBN: (纸本)0769525547

In this paper, we present and compare two methods for designing and profiling macro data flow graphs, which represent computation and communication patterns for the FDTD (Finite Difference Time Domain) problem in irregular computational areas. With the first method, optimized macro data flow graphs (MDFG) for FDTD computations are generated in three main phases: generation of initial MDFG based on wave propagation area partitioning, MDFG nodes merging with load balancing to obtain given number of macro nodes and communication optimization to minimize and balance internode data transmissions. With the second method, we use a modified CDC (Connectivity-based Distributed Node Clustering) algorithm to create an optimized macro data flow graph. The efficiency and execution time for both of these methods are compared. Computation efficiency for different several communication systems (MPI, RDMA RB, SHMEM) is discussed. All presented experimental results have been obtained by simulation.

关键词： data flow graphs

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Integration of energy reduction into high-level synthesis by partitioning

Integration of energy reduction into high-level synthesis by...

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5th IFIP TC 10 Working Conference on Distributed and Parallel Embedded Systems, DIPES 2006

作者： Rettberg, Achim Rammig, Franz Paderborn University Paderborn Germany

ISBN: (纸本)9780387393612

The optimization of power consumption at a very high design level is a critical step towards a power-efficient digital system design. The increasing usage of battery-powered and often wireless portable systems is driving the demand for IC and SoC devices consuming the smallest possible amount of energy. The aim of the method presented in this paper is to integrate low power methods within the scheduling process of the High-Level Synthesis by defining partitions. Starting from an Controlled-data-flow-Graph (CDFG) the proposed method uses standard scheduling techniques and path analysis on the graph to identify regions that can be combined to partitions. Each partition has a controlled activation or deactivation mechanism. That means, the partition can be switched off when it is not used. As an example design, a part of the MPEG-2 algorithm is used. © 2006 by International Federation for Information Processing.

关键词： data flow graphs

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An efficient on-line Approach for an On-chip HW/SW Partitioner and Scheduler

An efficient on-line Approach for an On-chip HW/SW Partition...

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19th International Conference on Architecture of Computing Systems, ARCS 2006

作者： Ghaffari, Fakhreddine Auguin, Michael I3S University ofNice Sophia Antipolis CNRS les Algorithmes bat. Euclide 2000 Route des Lucioles BP 121 Sophia-Antipolis06903 Cedex France Research Unit GMS National School of Engineers of Sfax SfaxBPW 3038 Tunisia

We describe here a new approach of On-line Partitioning Algorithm (O.P.A) which consists of adapting dynamically the architecture to the processing requirements. A scheduling heuristic is associated to this partitioning approach. We consider soft real time data flow graph oriented applications for which the execution time is dependent on the content of input data. We compare our method with an Off-line static HW/SW partitioning approach. We present results of the O.P.A on an image processing application. Our experiments included simulation results with SystemC for on-line scheduling and partitioning approaches. An ILP solver is used to compare the experiment results with an offline static HW/SW partitioning approach. © 2006 Gesellschaft fur Informatik (GI). All rights reserved.

关键词： data flow graphs

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RSVP II: A next generation automotive vector processor

RSVP II: A next generation automotive vector processor

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IEEE Intelligent Vechicles Symposium

作者： Chiricescu, S Chai, S Moat, K Lucas, B May, P Norris, J Essick, R Schuette, M Motorola Labs Schaumburg IL USA

ISBN: (纸本)0780389611

A large number of sensors (i.e., video, radar, laser, ultrasound, etc.) that continuously monitor the environment are finding their way in the average automobile. The algorithms processing the data captured by these sensors are streaming in nature and require a high rate of computation. Due to the characteristics of the automotive environment, this computation has to be delivered under very low energy and cost budgets. The Reconfigurable Streaming Vector Processing (RSVP'rm) architecture is a vector coprocessor architecture which accelerates streaming data processing. This paper presents the RSVP architecture and its second implementation, RSVP IL Our results show significant speedups on data streaming functions running compiled code. On a lane tracking application, RSVP H shows impressive performance results. From a performance/$ and performance/mW perspective, RSVP architecture compares favorably with leading DSP architectures. The time to market is substantially reduced due to ease of programmability, elimination of hand-tuned assembly code, and support for software re-use through binary compatibility across multiple implementations.

关键词： vector processor data flow graphs

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Optimal module and voltage assignment for low-power 05

Optimal module and voltage assignment for low-power

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10th Asia and South Pacific Design Automation Conference

作者： Chen, Deming Cong, Jason Xu, Junjuan Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90024 USA

ISBN: (纸本)0780387368

Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow graph under a dual-Vdd framework. We assume that each functional unit can be driven by a low Vdd or a high Vdd dynamically during run time to save dynamic power. We develop a polynomial-time optimal algorithm for assigning low Vdd to as many operations as possible under the resource and time constraint, and in the same time minimizing total switching activity through functional unit binding. Our algorithm shows consistent improvement over a design flow that separates voltage assignment from functional unit binding. We also change the initial scheduling to examine power-latency tradeoff scenarios. Experimental results show that we can achieve a 21% power reduction when latency bound is tight. When latency is relaxed by 10 to 100%, the power reduction is 31 to 73% compared to the synthesis results for the case of single high Vdd without latency relaxation. We also show comparison data of energy consumption under the same experimental setting.

关键词： high level synthesis circuit CAD low-power electronics circuit optimisation data flow graphs polynomials optimal module assignment optimal voltage assignment power consumption reduction high-level synthesis functional unit binding scheduled data flow graph dual-V/sub dd/ framework polynomial-time optimal algorithm total switching activity minimization power-latency tradeoff latency relaxation high level synthesis FUNCTIONAL UNITS data flow graphs circuit CAD Circuit optimization low-power electronics power reduction Polynomial Power consumption Latency LOW POWER Design flow

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Extended control flow graph based performance optimization using scratch-pad memory 05

Extended control flow graph based performance optimization u...

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Design, Automation and Test in Europe Conference and Exhibition (DATE 05)

作者： Pu, HL Ming, L Jing, J Southeast Univ Natl ASIC Syst Engn Technol Res Ctr Nanjing 210096 Peoples R China

ISBN: (纸本)0769522882

This paper presents an exploration approach for the researcher to choose the suitable size of Scratch-Pad memory (SPM)for maximal performance improvement of a specified application. The approach uses an extended control flow graph (ECFG) to describe the application and provides a solution to reduce the additional overhead of moving nodes to SPM. Experiments achieves on average 11 % increase in performance compared to the previous approaches and 44% decrease in the application's runtime compared to none SPM environment.

关键词： data flow graphs system-on-chip embedded systems performance evaluation storage management extended control flow graph performance optimization scratch-pad memory SoC

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Equalizing data-path for processing speed determination in block level pipelining

Equalizing data-path for processing speed determination in b...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Liang, XY Athalye, A Hong, S SUNY Stony Brook Dept Elect & Comp Engn Mobile Syst Design Lab Stony Brook NY 11794 USA

ISBN: (纸本)0780388348

Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware usign a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present in this paper a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.

关键词： data flow graphs

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