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12th ACM Great Lakes Symposium on VLSI, GLSVLSI 2002

作者： O'Neil, Timothy W. Sha, Edwin E.-H.M. Dept. of Computer Science and Engineering Univ. of Notre Dame Notre DameIN46556 United States Department of Computer Science Univ. of Texas at Dallas RichardsonTX75083 United States

ISBN: (纸本)1581134622

Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). In our previous work, we proposed a new technique, extended retiming, which can be combined with minimal unfolding to transform a DFG into one which is rate-optimal. The result, however, is a DFG with split nodes, a concise representation for pipelined schedules. This model and the extraction of the pipelined schedule it represents have heretofore not been explored. In this paper, we demonstrate one scheduling algorithm for such graphs, and then discuss a way to reduce the hardware requirements of the resulting schedule. In the process, we state and prove a tight upper bound on the minimum number of processors required to execute the static schedule produced by our algorithms. Finally, we demonstrate our methods on a specific example. Copyright 2002 ACM.

关键词： data flow graphs

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Temporal partitioning and scheduling data flow graphs for reconfigurable computers

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IEEE TRANSACTIONS ON COMPUTERS 1999年第6期48卷 579-590页

作者： Purna, KMG Bhatia, D Synopsys Inc Mountain View CA 94043 USA Univ Cincinnati Elect & Comp Engn & Comp Sci Dept Design Automat Lab Cincinnati OH 45521 USA

FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S-RPU and a computational task represented by an acyclic data now graph G = (V, E). Computations with logic area requirements that exceed S-RPU cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G = (V, E) such that each partitioned segment will not exceed S-RPU in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s(1), s(2), ..., s(k)}, scheduling assigns a unique ordering s(i) --> j, 1 less than or equal to i less than or equal to k, 1 less than or equal to j less than or equal to k, such that the comp

关键词： configurable computing field programmable gate arrays spatial partitioning temporal partitioning scheduling data flow graphs reconfigurable computers high performance computing

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Introducing redundant computations in RTL data paths for reducing BIST resources

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ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2001年第3期6卷 423-445页

作者： Parulkar, I Gupta, SK Breuer, MA Sun Microsyst Inc Palo Alto CA 94303 USA Univ So Calif Dept EE Syst Los Angeles CA 90089 USA

The need for considering BIST requirements during the scheduling and assignment stages of behavioral synthesis has been demonstrated in previous research and techniques for reducing BIST resources of a data path during these stages of synthesis have been developed. However, the degree of freedom that can be exploited during scheduling and assignment to minimize these resources is often limited by the data and control dependencies of a behavior. In this paper, we propose transformation of a behavior before scheduling and assignment, namely introducing redundant computations, such that the resulting data path is testable using few BIST resources. The transformation makes use of spare capacity of modules to add redundancy that enables test paths to be shared among the modules. A technique for identifying potential BIST resource sharing problems in a behavior and resolving them by redundant computation is presented. Introduction of redundant computations is performed without compromising the latency and functional resource requirement of the behavior.

关键词： behavioral synthesis built-in self-test data flow graphs redundant operations

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Heuristic datapath allocation for multiple wordlength systems

Heuristic datapath allocation for multiple wordlength system...

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Design, Automation and Test in Europe Conference and Exhibition (DATE 2001)

作者： Constantinides, GA Cheung, PYK Luk, W Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2BT England

ISBN: (纸本)0769509932;0769509940

This paper introduces a heuristic to solve the combined scheduling, resource binding, and wordlength selection problem for multiple wordlength systems. The algorithm involves an iterative refinement of operator wordlength information, leading to a scheduled and bound data-flow graph. Scheduling is performed with incomplete wordlength information during the intermediate stages of this refinement process. Results show significant area savings over known alterative approaches.

关键词： data flow graphs

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Estimation of program's quality on the base their structural-graphic representation 5

Estimation of program's quality on the base their structural...

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5th Korea-Russia International Symposium on Science and Technology, KORUS 2001

作者： Demin, A. Faculty of Automatics and Computer Technics Tomsk Polytechnic University Sovetskaya Street 84 Tomsk Russia

ISBN: (纸本)0780370082

One of problems of software design is the estimation of quality of the designed programs. Also estimation of quality of the programs is a major problem of software certification. Currently, in addition to the expert methods of quality estimation automatic methods are designed. These methods estimate the quality by using the complexity criterion of the programs. The integrated estimation of complexity uses three measures: nested structures, connection, and complexity of logic structure. To estimate using these measures the structural-graphic representation of the programs is used. To estimate the complexity the author uses the representation of the programs as a set of interrelated trees, data-flow graphs (DFG) and program flow diagrams. To obtain these estimations the special coefficients are introduced. The representation of the programs as DFGs allows to solve the problem of parallelization of the program on storage. © 2001 IEEE.

关键词： data flow graphs

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Adaptive negative cycle detection in dynamic graphs

Adaptive negative cycle detection in dynamic graphs

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2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

作者： Chandrachoodan, Nitin Bhattacharyya, Shuvra S. Liu, K. J. Ray Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States University of Maryland Institute for Advanced Computer studies United States

ISBN: (纸本)0780366859

We examine the problem of detecting negative cycles in a dynamic graph, which is a fundamental problem that arises in electronic design automation and systems theory. We introduce the concept of adaptive negative cycle detection, in which a graph changes over time, and negative cycle detection needs to be done periodically, but not necessarily after every individual change. Such scenarios arise, for example, during iterative design space exploration for hardware and software synthesis. We present an algorithm for this problem, called the Adaptive Bellman-Ford (ABF) algorithm, based on a novel extension of the well known Bellman-Ford algorithm. The ABF algorithm allows us to systematically adapt information for a given graph to a modified version of the graph. We show that the ABF algorithm significantly outperforms previously available approaches for dynamic graphs, which either recompute negative cycle information from scratch whenever a graph is modified, or process the modifications one at a time (incrementally). As an application of the ABF technique, we show that it can be used to obtain a very fast implementation of Lawler's technique for the computation of the maximum-cycle mean (MCM) of a graph, especially for a certain important kind of sparse graph. We further illustrate the application of the ABF technique to design-space exploration by developing automated search techniques for scheduling iterative data-flow graphs. © 2001 IEEE.

关键词： data flow graphs

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Heterogeneous multiprocessor for the management of real-time video and graphics streams

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2000年第11期35卷 1722-1731页

作者： Strik, MTJ Timmer, AH van Meerbergen, JL van Rootselaar, GJ Philips Res Labs NL-5656 AA Eindhoven Netherlands

This paper presents an application domain driven approach to the design of embedded systems on silicon, and it shea how this approach is used to design a chip for a multiwindow TV application. We discuss all major design steps in a logical order starting with an application domain analysis. This lead to the choice of Kahn data flow graphs as the programming paradigm for high-throughput signal applications. Based on this analysis we designed a multiprocessor architecture which uses run-time reconfiguration. Finally, attention is spent toward the physical implementation and the deep-submicron problems we had to solve. The result is a chip that can manage up to 25 internal real-time video streams. The chip combines the flexibility of a programmable solution with the cost effectiveness of a consumer product.

关键词： CMOS digital integrated circuits VLSI application specific integrated circuits circuit CAD computer graphic equipment data flow graphs digital signal processing chips embedded systems high level synthesis integrated circuit design multiprocessing systems computer graphic equipment Embedded systems Multiprocessing systems application specific integrated circuits circuit CAD integrated circuit design Very large scale integration consumer products digital signal processing chips data flow graphs CMOS digital integrated circuits high level synthesis

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data path placement with regularity

Data path placement with regularity

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IEEE/ACM International Conference on Computer Aided Design (ICCAD-2000)

作者： Ye, TT De Micheli, G Stanford Univ Dept Elect Engn Stanford CA 94305 USA

ISBN: (纸本)0780364457;0780364465

As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from data Plow Graph (DFG) and it is used for interconnect and congestion planning. A two step, heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.

关键词： data flow graphs

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Limits and graph structure of available instruction-level parallelism 6

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6th International Euro-Par 2000 Conference

作者： Stefanovic, D Martonosi, M Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)3540679561

We reexamine the limits of parallelism available in programs, using run-time reconstruction of program data-flow graphs. While limits of parallelism have been examined in the context of superscalar and VLIW machines, we also wish to study the causes of observed parallelism by examining the structure of the reconstructed data-flow graph. One aspect of structure analysis that we focus on is the isolation of instructions involved only in address calculations. We examine how address calculations present in RISC instruction streams generated by optimizing compilers affect the shape of the data-flow graph and often significantly reduce available parallelism.

关键词： data flow graphs

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On availability of bit-narrow operations in general-purpose applications 10th

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10th International Conference on Field-Programmable Logic and Applications, FPL 2000

作者： Stefanović, Darko Martonosi, Margaret Department of Electrical Engineering Princeton University PrincetonNJ08544 United States

ISBN: (纸本)3540678999

Program instructions that consume and produce small operands can be executed in hardware circuitry of less than full size. We compare different proposed models of accounting for the usefulness of bit-positions in operands, using a run-time profiling tool, both to observe and summarize operand values, and to reconstruct and analyze the program’s data-flow graph to discover useless *** find that under aggressive models, the average number of useful bits per integer operand is as low as 10, not only in kernels but also in general-purpose applications from SPEC95. © Springer-Verlag Berlin Heidelberg 2000.

关键词： data flow graphs

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