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Annual IEEE International ASIC/SOC Conference

作者： Pei-Qing Zou Chi-Ying Tsui Department of Electrical and Electronic Engineering Hong Kong University of Science and Technology Hong Kong China

ISBN: (纸本)0780365984

In this paper, we propose a technique to reduce the power consumption of the controller FSM of a data path in the specification level. Pattern extraction and sub-FSM creation are carried out during the synthesis of a datapath and the corresponding controller. The technique increases the number of zeros at the output of the main controller. Together with FSM partitioning technique, the new FSM specification will increase the occurrence of self-loop which results in a reduction of power consumption of the final controller implementation.

关键词： low-power electronics finite state machines logic partitioning probability clocks circuit optimisation data flow graphs logic simulation low power controller controller optimization data path pattern extraction FSM specification level sub-FSM creation partitioning technique self-loop

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Two-dimensional retiming

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1999年第2期7卷 198-211页

作者： Denk, TC Parhi, KK Broadcom Corp Irvine CA 92618 USA Univ Minnesota Dept Elect Engn Minneapolis MN 55455 USA

This paper considers two-dimensional (2-D) retiming, which is the problem of retiming circuits that operate on 2-D signals,We begin by discussing two types of parallelism available in 2-D data processing, which we call inter-iteration parallelism and inter-operation parallelism, We then present two novel techniques for 2-D retiming that can be used to extract inter-operation parallelism. These two techniques are designed to minimize the amount of memory required to implement a 2-D data-flow graph while maintaining a desired clock rate for the circuit. The first technique is based on an integer linear programming (ILP) formulation of the problem, and is called ILP 2-D retiming, This technique considers the entire 2-D retiming problem as a whole, but long central processing unit times are required if the circuit is large. The second technique, called orthogonal 2-D retiming, is a linear programming formulation which is derived by partitioning ILP 2-D retiming into two parts called s- and a-retiming. This technique finds a solution in polynomial time and is much faster than the ILP 2-D retiming technique, but the two sub-problems (s- and a-retiming) can give results which are not compatible with one another. To solve this incompatibility problem, a variation of orthogonal 2-D retiming called integer orthogonal 2-D retiming is developed. This technique runs in polynomial time and the s-retiming and a-retiming steps are guaranteed to give compatible results. We show that the techniques presented in this paper can result in memory hardware savings of 50% compared to previously published 2-D retiming techniques.

关键词： data flow graphs multidimensional signal processing parallel architectures retiming very large scale integration

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Extended retiming: Optimal scheduling via a graph-theoretical approach

Extended retiming: Optimal scheduling via a graph-theoretica...

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IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 99)

作者： O'Neil, TW Tongsima, S Sha, EHM Univ Notre Dame Dept Comp Sci & Engn Notre Dame IN 46556 USA

ISBN: (纸本)0780350413

Many iterative or recursive applications commonly found in DSP and image processing applications can be represented by data-flow graphs (DFGs). This graph is then used to perform DFG scheduling, where the starting times for executing the application's individual tasks are determined. The minimum length of time required to execute all tasks once is called the schedule length of the DFG. A great deal of research has been done attempting to optimize such applications by applying various graph transformation techniques to the DFG in order to minimize this schedule length. One of the most effective of these techniques is retiming. In this paper, we demonstrate that the traditional retiming technique does not always achieve optimal schedules and propose a new graph-transformation technique, extended retiming, which will. We will also present an algorithm for finding an extended retiming which transforms a DFG into one with minimal schedule length. Finally, we will demonstrate a constant-time algorithm which verifies the existence of a retimed DFG with the minimum schedule length.

关键词： data flow graphs

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Transformation of functional programs into data flow graphs implemented with PVM 3rd

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3rd European Conference on Parallel Virtual Machine, EuroPVM 1996

作者： Ebner, Ralf Pfaffinger, Alexander Institut für Informatik Technische Universität München MünchenD-80290 Germany

ISBN: (纸本)3540617795

We present an implementation of the functional language FASAN for automatic coarse-grain program parallelization on workstation clusters. It is designed primarily for recursive numerical algorithms with distributed tree-like data structures and it exploits the maximal inherent parallelism of a program. Based on the stream and data flow semantics of the language, the compiler generates C procedures for building the data flow graph as dynamic data structure. FASAN schedulers evaluate the function nodes in parallel, and provide for all necessary communication using the PVM library. The new concept of "wrapper streams" for tree data structures avoids superfluous synchronization. © Springer-Verlag Berlin Heidelberg 1996.

关键词： data flow graphs

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Synthesis of folded pipelined architectures for multirate DSP algorithms

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第4期6卷 595-607页

作者： Denk, TC Parhi, KK Broadcom Corp Irvine CA 92618 USA Univ Minnesota Dept Elect Engn Minneapolis MN 55455 USA

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues;The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms.

关键词： data flow graphs high-level synthesis parallel architectures retiming signal processing very large scale integration

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Exhaustive scheduling and retiming of digital signal processing systems

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 1998年第7期45卷 821-838页

作者： Denk, TC Parhi, KK Lucent Technol Bell Labs Holmdel NJ 07733 USA Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signal processing algorithms. In this paper, techniques are developed for generating all scheduling and retiming solutions for a strongly connected data-flow graph, allowing a designer to explore the space of possible implementations. Formulations are developed for two scheduling problems. The first scheduling problem assumes a bit-parallel target architecture. The formulation for this problem is general because it considers retiming the dataflow graph as part of scheduling, and this formulation reduces to the retiming formulation as a special case. The second scheduling problem assumes a bit-serial target architecture. Based on these formulations, the conditions for a legal scheduling solution are derived, and a systematic technique is presented for exhaustively generating all legal scheduling solutions for a strongly connected data-flow graph. Since retiming is a special case of scheduling, this systematic technique can also be used for exhaustively generating all legal retiming solutions. A technique is also developed for exhaustively generating only those bit-parallel schedules which satisfy a given set of resource constraints, The techniques for exhaustively generating scheduling and retiming solutions are demonstrated for several filters. For example, we show that a simple filter such as the biquad has 224 possible retiming solutions for a latency of one time unit. We also show that a fifth-order wave digital elliptic filter has 4.7 million and 580 million scheduling solutions for iteration periods of 17 and 18, respectively.

关键词： data flow graphs high-level synthesis parallel architectures retiming scheduling signal processing very large scale integration

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Rate optimal VLSI design from data flow graph 35

Rate optimal VLSI design from data flow graph

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35th Design Automation Conference

作者： Oh, M Ha, S Seoul Natl Univ Dept Comp Engn Kwanak Ku Seoul South Korea

ISBN: (纸本)0897919645

This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We propose a technique that inserts buffer registers to allow overlapped rate optimal implementation of VLSI. We illustrate that nonoverlapped schedules can be implemented by a simpler control path but with a larger unfolding factor, if exists, than overlapped schedules.

关键词： data flow graphs

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Nested loops optimization for multiprocessor architecture design

Nested loops optimization for multiprocessor architecture de...

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1998 Midwest Symposium on Circuits and Systems, MWSCAS 1998

作者： Leonardi, Andrea Passos, Nelson L. Sha, Edwin H-M. Dept. of Computer Science Midwestern State University Wichita FallsTX76308 United States Dept. of Computer Science and Engineering University of Notre Dame Notre DameIN46556 United States

ISBN: (纸本)0818689145

Multi-dimensional systems, including image processing, geophysical signal processing, and fluid dynamics, are becoming one of the most important targets of computational improvement studies. Most of the optimized solutions to those problems point to the use of application specific integrated circuits (ASICs). From the analysis of the multi-dimensional programming code, one can observe that nested loop like structures are often the most time consuming part. Designing ASICs with multiple processing units is usually the appropriate solution to achieve the required computational performance. In this paper, a new loop transformation algorithm, which allows an efficient utilization of the multiprocessor system is presented. Uniform nested loops are modeled as multi-dimensional data flow graphs. New loop structures are generated so that an arbitrary number of processors available in the system can run in parallel. An example demonstrates the effectiveness of the algorithm. © 1999 IEEE.

关键词： data flow graphs

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Structural BIST insertion using behavioral test analysis

Structural BIST insertion using behavioral test analysis

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European Design and Test Conference - ED and TC 97

作者： Nourani, M Papachristou, C Univ of Tehran Tehran Iran

ISBN: (纸本)0818677864

The purpose of this work is to develop a test synthesis technique based on BIST methodology which uses the test metrics (i.e. controllability and observability) obtained by lest analysis of the behavior to enhance the testability quality (fault coverage) of the corresponding structure and obtain the scheduled test behavior accordingly. The key feature of this work is in using the Structured data flow Graph (SDG) which annotates the behavioral information (e.g. data dependency) and structural information (e.g. binding, connectivity). To enhance testability of We structure, the SDG will be modified using transformation technique to improve the fault coverage and shorten the test schedule.

关键词： data flow graphs

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An ML-like module system for the synchronous language SIGNAL

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3rd International Conference on Parallel Processing, Euro-Par 1997

作者： Nowak, David Talpin, Jean-Pierre Gautier, Thierry P., Le Guernic IRISA INRIA-Rennes and CNRS Campus de Beaulieu F-35000 Rennes France

ISBN: (纸本)9783540634409

Synchronous languages, such as SIGNAL, are best suited for the design of dependable real-time systems. Synchronous languages enable a very high-level specification and an extremely modular implementation of complex systems by structurally decomposing them into elementary synchronous processes. Separate compilation in reactive languages is however made a difficult issue by global safety requirements. To enable separate compilation of the functional components of reactive systems while preserving their global integrity, we introduce a module system for SIGNAL. Just as data-types describe the invariants of program modules in functional languages, temporal and data-flow invariants interface SIGNAL processes to their environment. In conventional languages, typing is the medium allowing the separate compilation of functions in a program. In SIGNAL, the notion of conditional data-flow graph can similarly be used for separately compiling reactive processes and for assembling them in complex systems. Following this principle, we present the first design and implementation of a polymorphic type system and of a module system for the synchronous language SIGNAL.

关键词： data flow graphs

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