Given a behavioral description of an algorithm repretented by a data-flow graph, we show how to obtain a rateoptimal static schedule with the minimum unfolding factor under two timing models, integral grid model and f...
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An architecture synthesis environment oriented towards VLSI image processing systems is presented. The new method consists in synthesizing simultaneously data-path and control part of the architecture. The whole envir...
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This paper describes an alternative method for the scheduling of iterative data-flowgraphs. The method is based on the scheduling-range chart, which contains the information on the range within which each operation i...
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This paper describes an alternative method for the scheduling of iterative data-flowgraphs. The method is based on the scheduling-range chart, which contains the information on the range within which each operation in the graph can be scheduled. The scheduling range is determined by considering the intra- and inter-iteration precedence relations. The goal is to find an optimal position within the scheduling range of each operation in such a way that some quality criteria (number of hardware resources, iteration period, latency, register life-time) are optimized. A formal proof of the NP-completeness of the problem is given and two polynomial-time heuristics are introduced: fixed-rate (rate-optimal as a special case) scheduling where the number of hardware resources is optimized at the same time that a specific iteration period is guaranteed, and maximum-throughput scheduling with limited resources where the iteration period is optimized for a fixed number of processors. The algorithms are able to find optimal solutions for well-known benchmark examples.
This paper presents a systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified techn...
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This paper presents a systematic folding transformation technique to fold any arbitrary signal processing algorithm data-flow graph to a hardware data-flow architecture, for a specified folding set and specified technology constraints. The folding set specifies the processor in which and the time partition at which the task is executed. The folding set is typically obtained by performing scheduling and resource allocation for the algorithm data-flow graph and the specified iteration period. The technology constraints imposed on the hardware architecture (i.e., the level of pipelining and the implementation style of each processor) are also assumed to be known. The folding technique is used to derive the control circuitry of the hardware architecture (including registers, switches, and interconnections). We derive conditions for the validity of a specified folding set, and present approaches to generate the dedicated architecture using systematic folding of tasks to operators. We propose automatic retiming and pipelining of algorithms described by data-flowgraphs for folding. The folding algorithm is applied after preprocessing the data-flow graph (DFG) for automated pipelining and retiming. Our folding algorithm can accommodate single or multiple implementation styles and single or multiple computation clocks, and applies to folding of regular and irregular data-flowgraphs.
In behavioral synthesis, it is used to transform the description of the system into a dataflow graph (DFG) first, and then do scheduling and allocation. In our study, under the resource constraint, the fixed DFG with...
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Testability and diagnosability represent a mandatory step to be evaluated in the design of complex WSI (wafer scale integration) architectures before restructuring of the architecture to overcome defects can be perfor...
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ISBN:
(纸本)0818624825
Testability and diagnosability represent a mandatory step to be evaluated in the design of complex WSI (wafer scale integration) architectures before restructuring of the architecture to overcome defects can be performed. The authors propose a solution to such issues based on the analysis of testability and diagnosability of the dataflow graph derived from the algorithm that has to be implemented. The results of this analysis can show, even at this level, potential test and diagnosis problems in the final architecture. Guidelines to the architectural mapping are given to overcome such problems in the final architecture definition. The authors also present a testing and diagnosis approach that guarantees optical functional fault coverage under the single-error assumption.
A new approach is formulated for the synthesis of optimized pipelined data paths. The pipelined data paths are generated by first using a greedy algorithm and then applying a series of moves on the greedy solution to ...
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A data-driven multiprocessor architecture for rapid prototyping of complex DSP algorithms, based on direct execution of data-flowgraphs, is presented. High computation bandwidth is achieved by exploiting fine-grain p...
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In this paper we address methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the Minesota ARchitecture Synthesis (MARS) design system. We present new concurrent sche...
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An efficient decomposition technique that provides a more systematic approach in solving the optimal buffer assignment problem of an acyclic data-flow graph (ADFG) with a large number of computational nodes is present...
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An efficient decomposition technique that provides a more systematic approach in solving the optimal buffer assignment problem of an acyclic data-flow graph (ADFG) with a large number of computational nodes is presented. The buffer assignment problem is formulated as an integer linear optimization problem that can be solved in pseudopolynomial time. However, if the size of an ADFG increases, then integer linear constraint equations may grow exponentially, making the optimization problem more intractable. The decomposition approach utilizes the critical path concept to decompose a directed ADFG into a set of connected subgraphs, and the integer linear optimization technique can be used to solve the buffer assignment problem in each subgraph. Thus, a large-scale integer linear optimization problem is divided into a number of smaller-scale subproblems, each of which can be easily solved in pseudopolynomial time. Examples are given to illustrate the proposed decomposition technique.
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