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Numerical analysis of electrical defibrillation - The parallel approach

JOURNAL OF ELECTROCARDIOLOGY 1995年第sup1期28卷 15-20页

作者： Ng, KT Hutchinson, SA Gao, S SANDIA NATL LABS PARALLEL COMPUTAT SCI DEPT ALBUQUERQUE NM 87185 USA

Numerical modeling offers a viable tool for studying electrical defibrillation, allowing the behavior of field quantities to be observed easily as the different system parameters are varied. One numerical technique, namely the finite-element method, has been found particularly effective for modeling complex thoracic anatomies. However, an accurate finite-element model of the thorax often requires a large number of elements and nodes, leading to a large set of equations that cannot be solved effectively with the computational power of conventional computers. This is especially true if many finite-element solutions need to be achieved within a reasonable time period (eg, electrode configuration optimization). In this study, the use of massively parallel computers to provide the memory and reduction in solution time for solving these large finite-element problems is discussed. Both the uniform and unstructured grid approaches are considered. Algorithms that allow efficient mapping of uniform and unstructured grids to data-parallel and message-passing parallel computers are discussed. An automatic iterative procedure for electrode configuration optimization is presented. The procedure is based on the minimization of an objective function using the parallel direct search technique. Computational performance results are presented together with simulation results.

关键词： defibrillation finite-element method optimization data parallel message passing

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Analysis of data parallelism Methods with Deep Neural Network 22

Analysis of Data Parallelism Methods with Deep Neural Networ...

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Proceedings of the 2022 6th International Conference on Electronic Information Technology and Computer Engineering

作者： Ming Chen dept of Computer Science San Francisco State University United States

ISBN: (纸本)9781450397148

The deep neural network has significantly contributed to the detection, prediction, and classification aspects. Despite its emerging field, some flaws must be rectified to perform better. A problem with large datasets is that the model cannot be trained and tested rapidly, and the worst-case scenario is to have to wait hours for the result. Consequently, the paper evaluated the performance of two data parallelism methods and compared the situations of a diverse quantity of GPUs to decrease the model's testing time. Upon analyzing the consequences, it is evident that the communication overhead contributed to the low accuracy, even though it took less time to complete. An additional experiment involves increasing the number of times of testing to ensure accuracy and save time.

关键词： gradient descent distributed data parallel PyTorch data parallel

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Efficient Scheduling in Training Deep Convolution Networks at Large Scale

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IEEE ACCESS 2018年 6卷 61452-61456页

作者： Que, Can Zhang, Xinming Univ Sci & Technol China Sch Comp Sci & Technol Hefei 230027 Anhui Peoples R China

The deep convolutional network is one of the most successful machine learning models in recent years. However, training large deep networks is a time consuming process. Due to a large number of parameters in these networks, the efficiency of data parallel methods is usually limited by the communication speed of networks. In this paper, we introduce two new algorithms to speedup training large deep networks with multiple machines: 1) propose a new scheduling algorithm to reduce communication delay in gradient transmission and 2) present a new collective algorithm based on reverse-reduce tree to reduce link contentions. We implement our algorithms on a well-known library Caffe and obtain near linearly scaling performance on commodity Ethernet networks.

关键词： All reduce data parallel deep learning scheduling

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GPU accelerated radio astronomy signal convolution

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EXPERIMENTAL ASTRONOMY 2008年第1-2期22卷 129-141页

作者： Harris, Chris Haines, Karen Staveley-Smith, Lister Univ Western Australia Crawley WA 6009 Australia

The increasing array size of radio astronomy interferometers is causing the associated computation to scale quadratically with the number of array signals. Consequently, efficient usage of alternate processing architectures should be explored in order to meet this computational challenge. Affordable parallel processors have been made available to the general scientific community in the form of the commodity graphics card. This work investigates the use of the Graphics Processing Unit in the parallelisation of the combined conjugate multiply and accumulation stage of a correlator for a radio astronomy array. Using NVIDIA's Compute Unified Device Architecture, our testing shows processing speeds from one to two orders of magnitude faster than a Central Processing Unit approach.

关键词： correlation CUDA data parallel radio astronomy

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parallel Spatial Segmentation for the Automated Analysis of Football 4

Parallel Spatial Segmentation for the Automated Analysis of ...

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2015 4th International Work Conference on Bioinspired Intelligence (IWOBI)

作者： Siles, F. Saborio, J. C. Univ Costa Rica Sch Engn Dept Elect Engn PRIS Lab San Jose Costa Rica Ctr Nacl Alta Tecnol Colaboratorio Nacl Computac Avanzada San Jose Costa Rica

ISBN: (纸本)9781467378468

This work describes a computational methodology for the modelling and analysis of association football and its automatic interpretation. We describe several methods required to populate the modules of our purposed mathematical model, and provide empirical results of spatial segmentation on SD and HD videos in a multi-threaded, data-parallel computing environment.

关键词： Footballs automatic analysis segmentation Segmentation high definition video data parallel Modeling parallel Lines

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A Framework for Lattice QCD Calculations on GPUs

A Framework for Lattice QCD Calculations on GPUs

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IEEE 28th International parallel & Distributed Processing Symposium (IPDPS)

作者： Winter, F. T. Clark, M. A. Edwards, R. G. Joo, B. Thomas Jefferson Natl Accelerator Facil Newport News VA 23606 USA NVIDIA Corp Santa Clara CA 95050 USA

ISBN: (纸本)9780769552071

Computing platforms equipped with accelerators like GPUs have proven to provide great computational power. However, exploiting such platforms for existing scientific applications is not a trivial task. Current GPU programming frameworks such as CUDA C/C++ require low-level programming from the developer in order to achieve high performance code. As a result porting of applications to GPUs is typically limited to time-dominant algorithms and routines, leaving the remainder not accelerated which can open a serious Amdahl's law issue. The Lattice QCD application Chroma allows us to explore a different porting strategy. The layered structure of the software architecture logically separates the data-parallel from the application layer. The QCD data-parallel software layer provides data types and expressions with stencil-like operations suitable for lattice field theory. Chroma implements algorithms in terms of this high-level interface. Thus by porting the low-level layer one effectively ports the whole application layer in one swing. The QDP-JIT/PTX library, our reimplementation of the low-level layer, provides a framework for Lattice QCD calculations for the CUDA architecture. The complete software interface is supported and thus applications can be run unaltered on GPU-based parallel computers. This reimplementation was possible due to the availability of a JIT compiler which translates an assembly language (PTX) to GPU code. The existing expression templates enabled us to employ compile-time computations in order to build code generators and to automate the memory management for CUDA. Our implementation has allowed us to deploy the full Chroma gauge-generation program on large scale GPU-based machines such as Titan and Blue Waters and accelerate the calculation by more than an order of magnitude.

关键词： Application framework C++ CUDA GPU JIT Lattice QCD PTX Lattice QCD GRAPPER PICK UP Graphics Processing Unit Application Framework just in time compiler data parallel application layer Store management LOW LEVEL Code generation Chroma Frameworks software interface

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parallel Motion Compensation Interpolation in H.264/AVC using Graphic Processing Units

Parallel Motion Compensation Interpolation in H.264/AVC usin...

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International Conference on Industrial Control and Electronics Engineering (ICICEE)

作者： Zhang, Liye Wang, Jian Chu, Chen Ji, Xiaoyong Nanjing Univ Sch Elect Sci & Engn Nanjing Jiangsu Peoples R China

ISBN: (纸本)9780769547923

Motion compensation interpolation is an important part in H.264 codec. With the growing interest on high-definition (HD) contents, it is important to find methods to reduce the time cost of motion compensation interpolation which has greatly hindered the implementation of real time coding for HD contents. In this paper, a forward step is developed towards the implementation of interpolation algorithm into a Graphic Processing Units (GPU) using Compute Unified Device Architecture (CUDA). The proposed algorithm has achieved high parallelism on GPU at pixel level. Experimental results show our proposed solution on GPU can be up to 193.61% over traditional method on Central Processing Unit (CPU) without introducing any distortions and leads to a CPU usage reduction at the same time, since the massive parallel processing capability of GPU is efficiently harnessed.

关键词： motion compensation data parallel GPU

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Streamlining distributed Deep Learning I/O with ad hoc file systems

Streamlining distributed Deep Learning I/O with ad hoc file ...

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IEEE International Conference on Cluster Computing (Cluster)

作者： Schimmelpfennig, Frederic Vef, Marc-Andre Salkhordeh, Reza Miranda, Alberto Nou, Ramon Brinkmann, Andre Johannes Gutenberg Univ Mainz Mainz Germany Barcelona Supercomp Ctr BSC Barcelona Spain

ISBN: (纸本)9781728196664

With evolving techniques to parallelize Deep Learning (DL) and the growing amount of training data and model complexity, High-Performance Computing (HPC) has become increasingly important for machine learning engineers. Although many compute clusters already use learning accelerators or GPUs, HPC storage systems are not suitable for the I/O requirements of DL workflows. Therefore, users typically copy the whole training data to the worker nodes or distribute partitions. Because DL depends on randomized input data, prior work stated that partitioning impacts DL accuracy. Their solutions focused mainly on training I/O performance on a high-speed network but did not cover the data stage-in process, for example. We show in this paper that, in practice, (unbiased) partitioning is not harmful for distributed DL accuracy. Nevertheless, manual partitioning can be error prone and inefficient. Typically, data must be unpacked and shuffled before it is distributed to nodes. We propose a solution that features both: efficient stage-in and fast access to a global namespace to prevent biases. Our architecture is based around an ad hoc storage system relying on a high-speed interconnect allowing an efficient stage-in of DL data sets into a single global namespace. Our proposed solution does not limit access to parts of the data set or relies on data duplication, also relieving the HPC storage system. We obtain high I/O performance during training and ensure minimal interference with communication of the learning workers. The optimizations are transparent to DL applications and their accuracy is not affected by our architecture.

关键词： Deep Learning HPC file system data parallel

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Practically Private: Enabling High Performance CMPs Through Compiler-assisted data Classification 12

Practically Private: Enabling High Performance CMPs Through ...

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21st International Conference on parallel Architectures and Compilation Techniques (PACT)

作者： Li, Yong Melhem, Rami Jones, Alex K. Univ Pittsburgh Dept ECE Pittsburgh PA 15261 USA Univ Pittsburgh Dept CS Pittsburgh PA 15260 USA

ISBN: (纸本)9781450311823

State-of-the-art chip multiprocessor (CMP) proposals emphasize optimization to deliver computing power across many types of applications. Potentially significant performance improvements that leverage application specific characteristics such as data access behavior are missed by this approach. In this paper, we demonstrate that using fairly simple and inexpensive static analysis, data can be classified into private and shared. In addition, we develop a novel compiler-based approach to speculatively detect a third classification: practically private. We demonstrate that practically private data is ubiquitous in parallel applications and leveraging this classification provides opportunities to benefit performance. While this proposed data classification scheme can be applied to many micro-architectural constructs including the TLB, coherence directory and interconnect, we demonstrate its potential through an efficient cache coherence design. Specifically, we show that the compiler-assisted mechanism reduces an average of 46% coherence traffic and achieves up to 13%, 9%, and 5% performance improvement over shared, private, and state-of-the-art NUCA-based caching, respectively depending on scenarios.

关键词： data parallel Multi-threaded Applications Compilers Cache Coherence

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A high performance heterogeneous architecture and its optimization design

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2nd International Conference on High Performance Computing and Communications (HPCC 2006)

作者： Guo, Jianjun Dai, Kui Wang, Zhiying Natl Univ Def Technol Sch Comp Changsha 410073 Hunan Peoples R China

ISBN: (纸本)3540393684

The widely adoption of media processing applications provides great challenges to high performance embedded processor design. This paper studies a data parallel Coprocessor architecture based on SDTA and architecture decisions are made for the best performance/cost ratio. Experimental results on a prototype show that SDTA has high performance to run many embedded media processing applications. The simplicity and flexibility of SDTA encourages for further development for its reconfigurable functionality.

关键词： data parallel SDTA ASIP

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