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BitMine: An End-to-End Tool for Detecting Rowhammer Vulnerability

IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2021年 16卷 5167-5181页

作者： Zhang, Zhi He, Wei Cheng, Yueqiang Wang, Wenhao Gao, Yansong Wang, Minghua Li, Kang Nepal, Surya Xiang, Yang CSIRO Data61 Sydney NSW 2122 Australia Chinese Acad Sci Inst Informat Engn SKLOIS Beijing 100093 Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing 100049 Peoples R China NIO Shanghai 215332 Peoples R China Chinese Acad Sci Inst Informat Engn Beijing 100093 Peoples R China Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing 210094 Peoples R China Ant Grp Hangzhou 100020 Peoples R China Baidu Secur Beijing 100085 Peoples R China Swinburne Univ Technol Sch Software & Elect Engn Melbourne Vic 3122 Australia

Rowhammer is a destructive software-induced DRAM fault, which an attacker can leverage to break system security. Both individual customers and enterprise users (e.g., cloud providers) might refrain from using a computing system if it is vulnerable to rowhammer vulnerability. In this paper, we provide the first end-to-end tool, coined BitMine, that systematically assesses a DRAM chip's vulnerability to rowhammer bit flips. BitMine is an extension of DRAMDig. As DRAM address mappings are proprietary techniques and critical in inducing rowhammer bit flips, DRAMDig, our prior work, leverages domain knowledge to efficiently and deterministically reverse-engineer DRAM address mappings on Intel machines. By incorporating DRAMDig, BitMine configures three key parameters, i.e., hammer methods, hammer patterns, data patterns, on the effectiveness of finding rowhammer bit flips. BitMine by default implements 13 hammer methods, 4 hammer patterns and 16 data patterns and is extensible to support more. We evaluate DRAMDig and BitMine against multiple machine models that combine different DRAM chips and Intel microarchitectures. Our experiment results show that DRAMDig efficiently uncovers a deterministic DRAM address mapping for each machine model, and every implemented parameter in BitMine has its distinct effectiveness in triggering bit flips for different machine models.

关键词： Random access memory Tools Timing Microarchitecture Indexes Codes Security Rowhammer DRAM address mapping hammer method hammer pattern data pattern

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PCSG: pattern-Coverage Snippet Generation for RDF datasets 20th

PCSG: Pattern-Coverage Snippet Generation for RDF Datasets

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20th International Semantic Web Conference (ISWC)

作者： Wang, Xiaxia Cheng, Gong Lin, Tengteng Xu, Jing Pan, Jeff Z. Kharlamov, Evgeny Qu, Yuzhong Nanjing Univ State Key Lab Novel Software Technol Nanjing Peoples R China Univ Edinburgh Sch Informat Edinburgh Midlothian Scotland Robert Bosch GmbH Bosch Ctr Artificial Intelligence Gerlingen Germany Univ Oslo Dept Informat Oslo Norway

ISBN: (纸本)9783030883614;9783030883607

For reusing an RDF dataset, understanding its content is a prerequisite. To support the comprehension of its large and complex structure, existing methods mainly generate an abridged version of an RDF dataset by extracting representative data patterns as a summary. As a complement, recent attempts extract a representative subset of concrete data as a snippet. We extend this line of research by injecting the strength of summary into snippet. We propose to generate a pattern-coverage snippet that best exemplifies the patterns of entity descriptions and links in an RDF dataset. Our approach incorporates formulations of group Steiner tree and set cover problems to generate compact snippets. This extensible approach is also capable of modeling query relevance to be used with dataset search. Experiments on thousands of real RDF datasets demonstrate the effectiveness and practicability of our approach.

关键词： RDF data Snippet data pattern dataset search

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Anomaly detection of data and topology patterns in WSNs 17

Anomaly detection of data and topology patterns in WSNs

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17th Annual IEEE International Conference on Distributed Computing in Sensor Systems (IEEE DCOSS)

作者： Zakrzewski, Robert Martin, Trevor Oikonomou, George Univ Bristol Commun Syst & Networks Bristol Avon England Univ Bristol Artificial Intelligence Grp Bristol Avon England

ISBN: (纸本)9781665439299

Wireless sensor networks are often distributed which makes detection of cyber-attacks or misconfiguration hard. Topology and data patterns change may result from attacks leading to the compromise of data and service availability or indicate operational problems. Graphs are often used to model topology and data paths to describe and compare state of a system. For anomaly detection, the definition of normal patterns, deviation from normal, and criteria when to declare anomaly are required. In this contribution the process of acquisition of normal patterns (ground truth), and criteria when to declare anomaly based on graph comparison are proposed. The anomaly detection is suitable for deployment at the edge of a network. Finally, the inability to define all security threats is addressed by a custom tree-based classifier which only requires normal patterns for training. A simulated wireless sensor network was used to acquire data and apply the method. Our experiments show that data and topology change can be detected at the edge of a network.

关键词： Anomaly detection Machine learning Sensor network data pattern Topology Graph Cyber-security Fault detection

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CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read Power with Column data Segmentation 21

CDS-RSRAM: a Reconfigurable SRAM Architecture to Reduce Read...

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21st International Symposium on Quality Electronic Design (ISQED)

作者： Xu, Han Li, Ziru Qiao, Fei Wei, Qi Liu, Xinjun Yang, Huazhong Tsinghua Univ Beijing Peoples R China Beijing Natl Res Ctr Informat Sci & Technol Beijing Peoples R China

ISBN: (纸本)9781728142074

SRAM access takes a significant part of onchip power consumption in many signal processing systems. Reconfigurable data-adaptive SRAMs (RSRAM) can save considerable read power by utilizing data patterns. In these RSRAM designs, the column size (i.e., the number of cells in one column) of the cell array defines the granularity of data pattern exploitation. However, the column size cannot be too small due to circuit constraints, which makes finergrained data features hidden and suppresses RSRAM's advantage of low-power read. In this paper, we propose a reconfigurable SRAM architecture with column data segmentation (CDS-RSRAM) to break this limitation to exploit better data patterns without decreasing the column size. We partition data in one column into several segments and perform statistical analysis on every segment respectively. Each data segment has one exclusive flag bit to control its working mode while reading. This architecture can leverage data patterns at finer granularity and magnify RSRAM's advantage of low-power read. We also make a thorough overhead analysis and improve the mode decision strategy to minimize the power overheads. The simulation results show that compared with the original RSRAM, the proposed architecture saves up to 36.8% read power with 8.8% area overhead. Compared with 8T SRAM, the total power saving can be up to 77.1%.

关键词： Fine-grained SRAM data pattern data-adaptive

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data Mining pattern Valuation in Apparel Industry E-commerce Cloud

Data Mining Pattern Valuation in Apparel Industry E-commerce...

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2013 IEEE 4th International Conference on Software Engineering and Service Science

作者： Mingli Wu Hui Zhang Yebai Li College of Information Engineering North China University of Technology

ISBN: (纸本)9781467349994

For B2B（Business to Business） E-commerce systems in cloud environment,we propose a model for mining patterns in multi-databases in this *** gets the global pattern by analyzing local patterns globally,and then gets the high-vote pattern and exceptional *** to the difference between single-database and multi-databases,support in single-database only has local *** conception of weight is proposed,affiliating the factor of database itself,to make the pattern more comprehensive and effective.

关键词： multi-database data mining data pattern weight

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Speeding Up Crossbar Resistive Memory by Exploiting In-memory data patterns 17

Speeding Up Crossbar Resistive Memory by Exploiting In-memor...

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IEEE/ACM 36th International Conference on Computer-Aided Design (ICCAD)

作者： Wen, Wen Zhao, Lei Zhang, Youtao Yang, Jun Univ Pittsburgh Dept Elect & Comp Engn Pittsburgh PA 15260 USA Univ Pittsburgh Dept Comp Sci Pittsburgh PA 15260 USA

ISBN: (纸本)9781538630938

Resistive Memory (ReRAM) has emerged as a promising non-volatile memory technology that may replace a significant portion of DRAM in future computer systems. ReRAM has many advantages such as high density, low standby power and good scalability. ReRAM, when adopting crossbar architecture, has the smallest 4F2 planar cell size, which is ideal for constructing dense memory with large capacity. However, crossbar cell structure suffers from large sneak leakage and IR drop on long wires. To ensure operation reliability, ReRAM writes, in particular, RESET operations, conservatively use the worst-case access latency of all cells in ReRAM arrays, which leads to significant performance degradation and dynamic energy waste. In this paper, we study the correlation between the RESET latency and the number of cells in low resistant state (LRS) along bitlines, and propose to dynamically speed up ReRAM RESET operations for the rows that have small numbers of LRS cells. We leverage the intrinsic in-memory processing capability of ReRAM crossbar and propose a low overhead runtime profiler that effectively tracks the data patterns in different bitlines. To achieve further RESET latency reduction, we employ data compression and row address dependent data layout to reduce LRS cells on bitlines. The experimental results show that, on average, our design improves system performance by 20.5% and 14.2%, and reduces memory dynamic energy by 15.7% and 7.6%, compared to the baseline and the state-of-the-art crossbar design.

关键词： Resistive Memory data pattern Crossbar Array

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A Space-Filling Multidimensional Visualization (SFMDVis) for Exploratory data Analysis

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INFORMATION SCIENCES 2017年 390卷 32-53页

作者： Huang, Tze-Haw Huang, Mao Lin Quang Vinh Nguyen Zhao, Laiping Huang, Weidong Chen, Jinjun Univ Technol Sydney Sch Software FEIT POB 123 Broadway NSW 2007 Australia Univ Western Sydney Locked Bag 1797 South Penrith Dc NSW 1797 Australia Tianjin Univ Sch Comp Software China 92 Weijin Rd Tianjin Peoples R China Univ Tasmania Sch Engn & ICT Newnham Tas 7248 Australia

The space-filling visualization model was first invented by Ben Shneiderman [28] for maximizing the utilization of display space in relational data (or graph) visualization, especially for tree visualization. It uses the concept of Enclosure which dismisses the "edges" in the graphic representation that are all too frequently used in traditional node-link based graph visualizations. Therefore, the major issue in graph visualization which is the edge crossing can be naturally solved through the adoption of a space filling approach. However in the past, the space-filling concept has not attracted much attention from researchers in the field of multidimensional visualization. Although the problem of 'edge crossing' has also occurred among polylines which are used as the basic visual elements in the parallel coordinates visualization, it is problematic if those 'edge crossings' among polylines are not evenly distributed on the display plate as visual clutter will occur. This problem could significantly reduce the human readability in terms of reviewing a particular region of the visualization. In this study, we propose a new Space-Filling Multidimensional data Visualization (SFMDVis) that for the first-time introduces a space-filling approach into multidimensional data visualization. The main contributions are: (1) achieving the maximization of space utilization in multidimensional visualization (i.e. 100% of the display area is fully used), (2) eliminating visual clutter in SFMDVis through the use of the non-classic geometric primitive and (3) improving the quality of visualization for the visual perception of linear correlations among different variables as well as recognizing data patterns. To evaluate the quality of SFMDVis, we have conducted a usability study to measure the performance of SFMDVis in comparison with parallel coordinates and a scatterplot matrix for finding linear correlations and data patterns. The evaluation results have suggested that the accuracy

关键词： Multidimensional data visualization Space-filling data visualization Visual data analysis Linear correlation data pattern Usability study

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Quasi-Analytical Model of 3-D Vertical-RRAM Array Architecture for MB-Level Design

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2017年第4期64卷 1568-1574页

作者： Li, Zhiwei Chen, Pai-Yu Liu, Haijun Li, Qingjiang Xu, Hui Yu, Shimeng Natl Univ Def Technol Coll Elect Sci & Engn Changsha 410073 Hunan Peoples R China Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size.

关键词： 3-D integration cross-point array data pattern nonlinearity resistive random access memory (RRAM) sneak path

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Creation of data pattern for High Accuracy Flying Height Measurement

Creation of Data Pattern for High Accuracy Flying Height Mea...

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9th Perpendicular Magnetic Recording Conference (PMRC)

作者： Tang, Yawshing Lee, Sung-Chang Suk, Mike Samsung Informat Syst Amer San Jose CA 95134 USA

A common technique for measuring flying height is using the ratio of the 1(st) and the 3(rd) harmonic of a periodic data pattern. Since the 3(rd) harmonic is typically smaller than the 1(st), and the recording channel usually rolls off at higher harmonics, the magnitude of the 3(rd) harmonic dominates the signal to noise ratio of the measured flying height. Therefore it is desirable to create a data pattern that has a large 3(rd) harmonic component for flying height measurement. This paper describes a method to create data patterns with a high frequency component larger than the 1(st) harmonic. The method multiplies a high frequency signal to a basic periodic signal to create a high frequency component and a low frequency component. The high frequency signal may be the 3(rd) harmonic and can be larger than the low frequency one. In addition, newly created data pattern was applied to real hard disk drive, and the accuracy of measured flying height was demonstrated in comparison with measured flying height based on conventional data pattern. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of the Organising Committee of the 9th Perpendicular Magnetic Recording Conference

关键词： data pattern flying height flying clearance head-disk interface (HDI) thermal flying-height control (TFC)

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Dec :: Pdp11 :: Xxdp :: Fiche 200Dpi :: 0062 Cndmaa0 Dmv11Uctl

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2016年

Dec :: Pdp11 :: Xxdp :: Fiche 200Dpi :: 0062 Cndmaa0 Dmv11Uctl by published by

关键词： 200dpi bcc bcc error cndmaa0 data data pattern dmv11uctl error error escape error message escape escape tst exit fiche jsr master clear mctrl diag mov mov mov pdp11 test test trap trap trap trap tst

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