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2nd International Conference for Convergence in Technology (I2CT)

作者： Sarkar, Subhra J. Kundu, Palash K. Sarkar, Gautam Techno India Batanagar Dept Elect Engn Kolkata India Jadavpur Univ Dept Elect Engn Kolkata India

ISBN: (纸本)9781509043071

Generally lossless compression techniques can give lower compression ratio. In this paper, an alternative scheme is tailored to compress generation scheduling information. It can reduce the data volume by 90% or even more for majority of the available scheduling data. While approaching towards the formation of smart grid, data management is extremely important. This low computational novel algorithm, DBEA can serve the purpose and can be embedded at microcontroller level to develop a smart autonomous system dealing with generation scheduling data. DBEA is developed and tested in C and MATLAB environment to obtain the results. The compression ratio achieved by the algorithm is promising and is comparable to the existing algorithm in other application domain. But the algorithm can he used for selected arrays only, particularly scheduling information array which is the limitation of the algorithm.

关键词： Differential Binary Encoding Algorithm (DBEA) Compression data array Generating Station Scheduling Load Dispatch Centre (LDC)

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Basic Arithmetic Coding based Approach for Compressing Generation Scheduling data array

Basic Arithmetic Coding based Approach for Compressing Gener...

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IEEE Calcutta Conference (CALCON)

作者： Sarkar, Subhra J. Kar, Kalyan Das, Indranil Techno India Batanagar Dept Elect Engn Kolkata India

ISBN: (纸本)9781538637456

Generation scheduling is very important for maintaining the stability of power system. Generation of any unit or plant is varied according to the scheduling chart prepared by the load dispatch centre (LDC). For proper handling of this large data array, it is important to reduce the bulk volume of information by proper compression algorithm. In that context, an simple approach based on Basic Arithmetic Coding is developed in MATLAB environment to compress the large scheduling data array. The compression ratio being obtained for various set of scheduling data is high which implies reduced memory requirement for storing the encrypted information and reduced characters for transmitting the information. Compression ratio being obtained varies with number of digits of elements in data array and highest value is obtained with 3-digit elements. The work is scalable for compressing parameter monitoring data as well and similar results can be obtained with this enormous volume of data as well.

关键词： data Compression Basic Arithmetic Coding Scheduling data array Compressed array

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A Novel Huffman Coding based Approach to Reduce the Size of Large data array

A Novel Huffman Coding based Approach to Reduce the Size of ...

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IEEE International Conference on Circuit, Power and Computing Technologies (ICCPCT)

作者： Sarkar, Subhra J. Sarkar, Nabendu Kr. Banerjee, Aritra Batanagar Inst Engg Management & Sci Dept Elect Engn Kolkata India Haldia Inst Technol Dept Elect Engn Haldia India

ISBN: (纸本)9781509012770

While dealing with large data array required in various applications, the memory required for the data storage and data transfer of that bulk data becomes difficult. If the array size can be reduced without losing the data, the problem of storage and data transfer can be avoided. In this paper, a Huffman Coding based data compression algorithm is proposed and tested in MATLAB environment which will significantly reduce the size of one dimensional data array. Though the algorithm is tested with number array only, the algorithm can be extended to be applied with character array with slight modification.

关键词： data Compression Huffman Coding data array Compressed array

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A Novel Huffman Coding based Approach to Reduce the Size of Large data array

A Novel Huffman Coding based Approach to Reduce the Size of ...

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International Conference on Circuits, Power and Computing Technologies

作者： Subhra J. Sarkar Nabendu Kr. Sarkar Aritra Banerjee Department of Electrical Engineering Batanagar Institute of Engg. Management and Science Kolkata India Department of Electrical Engineering Haldia Institute of Technology Haldia India

ISBN: (纸本)9781509012787

关键词： data Compression Huffman Coding data array Compressed array

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Possibility of Predicting the Fracture of Metallic Materials with a Heterogeneous Structure

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RUSSIAN METALLURGY 2022年第10期2022卷 1318-1331页

作者： Kudrya, A., V Sokolovskaya, E. A. Tang, V. F. Natl Univ Sci & Technol MISiS Moscow 119049 Russia

The approaches to predicting the fracture of metallic materials with a heterogeneous structure are analyzed. Joint measurements of the geometry of structural elements, their relative location (configuration), and fracture morphology at macro-, meso-, and microscale levels are shown to be necessary to estimate the risk of fracture along with the detection of acoustic emission with allowance for the statistical nature of the objects to be analyzed. Representative results can be obtained using digital technologies and Big data algorithms.

关键词： fracture heterogeneous structures strength ductility toughness fracture toughness quantitative fractography acoustic emission data array digital technologies

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Touche: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads 52

Touche: Towards Ideal and Efficient Cache Compression By Mit...

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52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hong, Seokin Abali, Bulent Buyuktosunoglu, Alper Healy, Michael B. Nair, Prashant J. Kyungpook Natl Univ Daegu South Korea IBM TJ Watson Res Ctr Yorktown Hts NY USA Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781450369381

Compression is seen as a simple technique to increase the effective cache capacity. Unfortunately, compression techniques either incur tag area overheads or restrict cache block placement to only include neighboring addresses. Ideally, we should be able to place compressed cache blocks without any restrictions or overheads. This paper proposes Touche, a framework for storing multiple compressed blocks from arbitrary addresses within a cacheline without tag area overheads. The Touche framework consists of three components. The first component, called the "Signature" (SIGN) engine, creates shortened signatures from the tag addresses of compressed blocks. Due to this, the SIGN engine can store multiple signatures in each tag entry. On a cache access, the physical cacheline is accessed only if there is a signature match (which has a negligible probability of false positive). The second component, called the "Tag Appended data" (TADA) mechanism, stores the full tag addresses with data. TADA enables Touche to detect false positive signature matches by providing the full tag address. The third component, called the "Superblock Marker" (SMARK) mechanism, uses a unique marker in the tag entry to indicate compressed cache blocks from neighboring physical addresses in the same cacheline. Touche is hardware-based and achieves an average speedup of 12% (ideal 13%) when compared to an uncompressed baseline.

关键词： Compression Caches Tag array data array Hashing

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Bd Software :: Bds C File Io Primer

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2016年

Bd Software :: Bds C File Io Primer by published by

关键词： abort bds buffer buffered correct number data data array disk file file descriptor functions input file output file primer printf raw raw file raw functions software text file

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Dec :: Tech Reports :: Wrl-Tn-4

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2016年

[Auto Generated] 1. Introduction 1 2. Concepts 1 3. Protocols 1 3.1. Record and data formats 2 3.2. Printserver Protocol 2 3.3. Printer management protocol 5 4. Examples 10

关键词： client data data array error messages file management management client management clients master management print print job print server printer printserver printserver protocol protocol reply reports server server protocol soj data wrl-tn-4

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Generation of Memory Architecture in Operator Design Methodology

Generation of Memory Architecture in Operator Design Methodo...

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2011 International Conference on Intelligent Computing and Integrated Systems(ICISS 2011)

作者： Shuangxi Gao, Teng Wang, Xin’an Wang, Ziyi Hu Key Lab of Integrated Microsystem Peking University Shenzhen Graduate School Shenzhen, China Hui Fan School of Computer and Information Technology Beijing Jiaotong University Beijing, China

Nowadays, traditional ASIC design methodology shows its limitations to meet the short time-to-market which is the hallmark of modern consumer electronic products, and great interests have been focused on high-level synthesis (HLS) in the past two decades. In this paper, the scheme for generation of the memory architecture in a novel HLS method named operator design methodology is proposed. The principle and process of operator design methodology is first presented, then the steps of mapping the data array and pointer in C description to the memory model in hardware description is demonstrated, finally a hardware implementation of a target algorithm is conducted based on the proposed memory generation scheme and the experiment results is compared with that of the SPARK tool by UC San Diego, which presents an 65% increase in the performance and 30% reduction in hardware cost under the constraint of 100MHz clock frequency.

关键词： operator design methodology hign-level synthesis memory architecture data array

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An algorithm for three-way data analysis that alternatively minimizes coupled vector (COV) resolution error and PARAFAC error

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ANALYTICAL SCIENCES 2003年第5期19卷 753-756页

作者： Cao, YZ Chen, H Wu, HL Yu, RQ China Natl Packaging Corp Zhuzhou Inst Technol Key Lab New Packaging Mat & Technol Zhuzhou 412008 Peoples R China Environm Monitoring Cent Stn Guangzhou City Guangzhou 510030 Peoples R China Hunan Univ Coll Chem & Chem Engn Changsha 410082 Peoples R China

A novel algorithm, alternatively minimizing coupled vector (COV) resolution error and PARAFAC error algorithm, is proposed in this paper. This algorithm can overcome the problem of slow convergence and is insensitive to the estimation of component number, such problems are unavoidable while using the traditional parallel factors analysis (PARAFAC) algorithm. In other words, this algorithm is capable of improving the computing speed and providing accurate resolutions provided that the number of factors used in the computation is no less than that of the actual underlying ones. The characteristic performances were demonstrated with a novel fluorescence data array.

关键词： .data analysis Three-way alternatively slow convergence Coupled Vector Resolution Error component number PARAFAC algorithm computing speed data array

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