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IEEE 18th International Conference on Parallel and Distributed Systems (ICPADS)

作者： Wang, Lizhe Chen, Dan Ranjan, Rajiv Khan, Samee U. Kolodziej, Joanna Wang, Jun Chinese Acad Sci Ctr Earth Observat & Digital Earth Beijing 100864 Peoples R China China Univ Geosciences Sch Comp Beijing Peoples R China CSIRO ICT Ctr Informat Engn lab Marshfield 2122 WI USA N Dakota State Univ Dept Elect & Comp Engn Grand Forks ND 58201 USA Univ Technol Inst Comp Sci Krakow Poland Univ Cent Florida Dept Elect Engn & Comp Sci Orlando FL 32816 USA

ISBN: (纸本)9781467345651;9780769549033

Analysis of neural signals like electroencephalogram (EEG) is one of the key technologies in detecting and diagnosing various brain disorders. As neural signals are non-stationary and non-linear in nature, it is almost impossible to understand their true physical dynamics until the recent advent of the Ensemble Empirical Mode Decomposition (EEMD) algorithm. The neural signal processing with EEMD is highly compute-intensive due to the high complexity of the EEMD algorithm. It is also data-intensive because 1) EEG signals contain massive data sets 2) EEMD has to introduce a large number of trials in processing to ensure precision. The MapReduce programming mode is a promising parallel computing paradigm for data intensive computing. To increase the efficiency and performance of the neural signal analysis, this research develops parallel EEMD neural signal processing with MapReduce. In this paper, we implement the parallel EEMD with Hadoop in a modern cyberinfrastructure. Test results and performance evaluation show that parallel EEMD can significantly improve the performance of neural signal processing.

关键词： data-intensive computing MapReduce parallel processing PARALLEL PROCESSING (COMPUTERS) signal processing Electroencephalography Brain Diseases Key technology MAPPING(MATHEMATICAL) Signal analysis data parallel computing data flow computing

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Strengthening data and Research Tools on Migration and Development

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INTERNATIONAL MIGRATION 2009年第5期47卷 3-22页

作者： Black, Richard Skeldon, Ronald Univ Sussex Sussex Ctr Migrat Res Brighton E Sussex England

This paper reviews available data sources for the study of migration and development through both retrospective and continuous data collection systems. It is argued that much basic data already exists for the study of international migration but that the addition of a relatively small number of simple, although not necessarily cheap measures can be taken to improve existing data. The priority is to generate flow data between countries for recent time periods and the paper makes suggestions how this can be best achieved. The paper goes on to an assessment of the types and availability of data needed to understand better the relationships between migration and development more broadly. data at several scales, macro and micro, and for a variety of types of migration will be required in order to achieve this objective, particularly if less visible flows, such as those internal to developing countries, or those involving women, are to be better understood. The paper concludes by moving beyond the traditional state-led data-gathering systems to examine the potential for civil society organizations to help in strengthening data and research on migration and development.

关键词： MIGRANT labor TRANSBORDER data flow ECONOMIC development COMPUTER network resources data mining FOREIGN workers RESEARCH CONTRACT employment data flow computing AUTOMATIC data collection systems ECONOMIC aspects DEVELOPING countries

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Force-Directed Scheduling for data flow Graph Mapping on Coarse-Grained Reconfigurable Architectures

Force-Directed Scheduling for Data Flow Graph Mapping on Coa...

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2014 International Conference on Reconfigurable computing and FAGAs

作者： Fell, Alexander Rakossy, Zoltan Endre Chattopadhyay, Anupam Indraprastha Inst Informat Technol New Delhi India Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany Nanyang Technol Univ Sch Comp Engn Singapore Singapore

ISBN: (纸本)9781479959440

In terms of energy and flexibility, Coarse-Grained Reconfigurable Architectures (CGRA) are proven to be advantageous over fine-grained architectures, massively parallel GPUs and generic CPUs. However the key challenge of programmability is preventing wide-spread adoption. To exploit instruction level parallelism inherent to such architectures, optimal scheduling and mapping of algorithmic kernels is essential. Transforming an input algorithm in the form of a data flow Graph (DFG) into a CGRA schedule and mapping configuration is very challenging, due the necessity to consider architectural details such as memory bandwidth requirements, communication patterns, pipelining and heterogeneity to optimally extract maximum performance. In this paper, an algorithm is proposed that employs Force-Directed Scheduling concepts to solve such scheduling and resource minimization problems. Our heuristic extensions are flexible enough for generic heterogeneous CGRAs, allowing to estimate the execution time of an algorithm with different configurations, while maximizing the utilization of available hardware. Beside our experiments, we compare also given CGRA configurations introduced by state-of-the-art mapping algorithms such as EPIMap, achieving optimal resource utilization by our schedule with a reduced overall DFG execution time by 39% on average.

关键词： data flow computing reconfigurable architectures resource allocation scheduling CGRA DFG coarse-grained reconfigurable architecture data flow graph mapping force-directed scheduling resource minimization Algorithm design and analysis Fabrics Hardware Indexes Pipelines Schedules Scheduling

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Energy Efficient data flow Transformation for Givens Rotation based QR Decomposition

Energy Efficient Data Flow Transformation for Givens Rotatio...

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Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Sharma, Namita Panda, Preeti Ranjan Li, Min Agrawal, Prashant Catthoor, Francky Indian Inst Technol Delhi New Delhi India IMEC Leuven Belgium

ISBN: (纸本)9783981537024

QR Decomposition (QRD) is a typical matrix decomposition algorithm that shares many common features with other algorithms such as LU and Cholesky decomposition. The principle can be realized in a large number of valid processing sequences that differ significantly in the number of memory accesses and computations, and hence, the overall implementation energy. With modern low power embedded processors evolving towards register files with wide memory interfaces and vector functional units (FUs), the data flow in matrix decomposition algorithms needs to be carefully devised to achieve energy efficient implementation. In this paper, we present an efficient data flow transformation strategy for the Givens Rotation based QRD that optimizes data memory accesses. We also explore different possible implementations for QRD of multiple matrices using the SIMD feature of the processor. With the proposed data flow transformation, a reduction of up to 36% is achieved in the overall energy over conventional QRD sequences.

关键词： MIMO communication data flow computing energy conservation matrix decomposition optimisation Givens Rotation QR decomposition SIMD data memory access energy efficient data flow transformation matrix decomposition algorithm Computer architecture Matrix converters Matrix decomposition Program processors Registers Sequential analysis Vectors

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Model Selection and data Assembly for Power System Simulations

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IEEE Power Engineering Review 1982年第9期PER-2卷 52-53页

作者： Undrill, J.M. Laskowski, T.F. Power Technologies Inc. Schenectady NY United States

While the theory of rotating machine modeling has been fully developed for many years, the use of overly simplified models that were adopted originally because of computational limitations persists in many programs and data bases, even though the computational limitations no longer exist. Lack of refined equipment data and concern over the applicability of typical parameter values where specific values are unavailable have been significant factors inhibiting the use of comprehensive rotating machine modeling. This paper discusses some aspects of system dynamic performance whose proper simulation requires comprehensive machine modeling and illustrates the sensitivity of simulation results to the values of some of the parameters for which specific values are often unavailable It argues that the use of properly chosen comprehensive generator and motor models gives superior results to those obtained with simplified models even when exact parameter values are unavailable and assumed parameter values must be used. Copyright © 1982 by The Institute of Electrical and Electronics Engineers, Inc.

关键词： Power system modeling Assembly systems Power system simulation Electromagnetic modeling Computer simulation data flow computing Computational modeling System testing Transformers Character generation

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Performance and Operational Experience with the Heterogeneous Farm of the ATLAS Trigger and data Acquisition System

Performance and Operational Experience with the Heterogeneou...

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IEEE Nuclear Science Symposium/Medical Imaging Conference (NSS/MIC)/18th International Workshop on Room-Temperature Semiconductor X-Ray and Gamma-Ray Detectors

作者： Pasqualucci, Enrico Ist Nazl Fis Nucl Sez Roma I-00185 Rome Italy

ISBN: (纸本)9781467301206

The ATLAS trigger and data acquisition (TDAQ) is a distributed, multi trigger level, data-acquisition system, mostly made of off-the-shelf processing units organized in a farm. In its final configuration the system will account more than 2000 nodes, having heterogeneous capabilities and network connections, due to the TDAQ program for rolling expansions and upgrades. In this paper we present how we dealt with the farm heterogeneity during the proton-proton collisions of 2010 and 2011: a period characterized by changing working conditions, and constantly increasing LHC instantaneous luminosity. We describe a graphical tool to balance the computing-power and bandwidth sharing across the trigger farms, a data-flow monitoring daemon that provides high-level resource-aware data-flow operational information and the evolution of data-flow communication protocols.

关键词： ATLAS trigger and data acquisition LHC instantaneous luminosity Physics Protocols TDAQ program bandwidth sharing computing-power data acquisition data flow computing data-flow communication protocols data-flow monitoring daemon distributed multitrigger level data-acquisition system farm heterogeneity graphical tool high energy physics instrumentation computing high-level resource-aware data-flow operational information network connections off-the-shelf processing units operational experience position sensitive particle detectors protocols proton+proton collisions rolling expansions trigger circuits working conditions

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Verilog-based simulation of hardware support for data-flow concurrency on Multicore systems

Verilog-based simulation of hardware support for Data-flow c...

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13th International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Matheou, George Evripidou, Paraskevas Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781479901036

data-Driven Multithreading (DDM) is a threaded data-flow model that schedules threads for execution based on data availability. DDM is utilizing a Thread Scheduling Unit (TSU) for the management of the threads on sequential processors. In this work we present the hardware implementation of the TSU with synthesizable code using the Verilog HDL and its evaluation using the ISim simulator. The evaluation results show that the TSU is able to run at a maximum frequency of 180 MHz and consumes only 5% of the Xilinx Virtex-6 FPGA resources. The initial results obtained in this work will enable us to design an FPGA based DDM multicore chip consisting of several Microblaze cores driven by the TSU. Thus, we will be able to evaluate the performance of the novel threaded data-flow model and have direct comparison with the sequential model on the same hardware.

关键词： data flow computing field programmable gate arrays hardware description languages integrated circuit design microprocessor chips multiprocessing systems performance evaluation processor scheduling

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data flow algorithms for processors with vector extensions: handling actors with internal state

Data flow algorithms for processors with vector extensions: ...

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IEEE Global Conference on Signal and Information Processing (GlobalSIP)

作者： Barford, Lee Bhattacharyya, Shuvra S. Liu, Yanzhou Keysight Technol Keysight Labs Reno NV USA Univ Maryland College Pk MD 20742 USA

ISBN: (纸本)9781479970889

Full use of the parallel computation capabilities of present and expected CPUs and GPUs require use of vector extensions. Yet many actors in data flow systems for digital signal processing have internal state (or, equivalently, an edge that loops from the actor back to itself) that impose serial dependencies between actor invocations that make vectorizing across actor invocations impossible. Ideally, issues of inter-thread coordination required by serial data dependencies should be handled by code written by parallel programming experts that is separate from code specifying signal processing operations. The purpose of this paper is to present one approach for so doing in the case of actors that maintain state. We propose a methodology for using the parallel scan (also known as prefix sum) pattern to create algorithms for multiple simultaneous invocations of such an actor that results in vectorizable code. Two examples of applying this methodology are given: (1) infinite impulse response filters and (2) finite state machines. The correctness and performance of the resulting IIR filters are studied.

关键词： digital signal processing data flow computing vector processors parallel algorithms

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Structure Matters A new Approach for data flow Tracking

Structure Matters A new Approach for Data Flow Tracking

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35th IEEE-Computer-Society Workshop on Security and Privacy (SP)

作者： Lovat, Enrico Kelbert, Florian Tech Univ Munich Garching Germany

ISBN: (纸本)9781479951031

Usage control (UC) is concerned with how data may or may not be used after initial access has been granted. UC requirements are expressed in terms of data (e.g. a picture, a song) which exist within a system in forms of different technical representations (containers, e.g. files, memory locations, windows). A model combining UC enforcement with data flow tracking across containers has been proposed in the literature, but it exhibits a high false positives detection rate. In this paper we propose a refined approach for data flow tracking that mitigates this overapproximation problem by leveraging information about the inherent structure of the data being tracked. We propose a formal model and show some exemplary instantiations.

关键词： data flow analysis data flow computing UC enforcement containers data access data flow tracking false positive detection rate formal model information leveraging inherent data structure over-approximation problem mitigation technical representations usage control Containers data models Discrete Fourier transforms Operating systems Postal services Security Semantics data structure CONTAINERS data structures data flow analysis discrete Fourier transform Operating systems data models Access to Information information retrieval data flow Postal Service Semantics e mail service

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An O(N) supply voltage assignment algorithm for low-energy serially connected CMOS modules and a heuristic extension to acyclic data flow graphs

An O(N) supply voltage assignment algorithm for low-energy s...

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IEEE-Computer-Society Annual Symposium on VLSI

作者： Diril, AU Dhillon, YS Choi, KW Chatterjee, A Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)0769519040

In this paper, a novel algorithm is proposed for assigning supply voltages to serially executing functional units (FUs) in a digital system such that the overall dynamic energy consumption is minimized for a given timing constraint. Novel closed form expressions for optimum. Supply voltage values are presented. The computation time of the algorithm is O(N) for N FUs in series. An extension of the O(N) algorithm is proposed for optimizing the acyclic data flow graph associated with any given task. Given the number of FUs available for the task the operations required for the task are scheduled on the FUs. Voltages are then assigned to the FUs on each path of the flow graph using the O(N) algorithm. Energy savings of 10-60% are achieved on DSP filter designs using the proposed high-level optimization methodology over single supply voltage designs.

关键词： data flow computing Delay Digital systems Dynamic voltage scaling Energy consumption flow graphs Frequency Iterative algorithms Scheduling algorithm Timing

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