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17th International Conference on Advanced Information Networking and Applications

作者： Liu, SY Hosei Univ Fac Comp & Informat Sci Dept Comp Sci Tokyo Japan

ISBN: (纸本)0769519067

Condition data flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon data flow Diagrams, Petri Nets, and pre-post notation. They are used in the SOFL (Structured Object-Oriented Formal Language) specification language to describe the architecture of formal specifications for network protocols and general dependable systems by defining data flow communications among processes. A large-scale specification is usually modeled as a hierarchy of CDFDs resulting from decomposing processes at various levels into CDFDs. To ensure that a decomposed CDFD is correct with respect to its high level process, verification is essential. However, how to verify rigorously the correctness of CDFDs is still an open problem. In this paper we address this problem by establishing a logical system consisting of inference rules for reasoning about CDFDs, and putting forward both formal proof and specification simulation as potential methods for correctness verification. We also give algorithms for deriving pre and postconditions of CDFDs and examples of verifying their correctness.

关键词： Computer networks Computer science data flow computing Formal languages Formal specifications Formal verification Large-scale systems Petri nets Protocols Uniform resource locators

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Spatial Cluster Detection in Spatial flow data

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GEOGRAPHICAL ANALYSIS 2016年第4期48卷 355-372页

作者： Tao, Ran Thill, Jean-Claude Univ North Carolina Charlotte Dept Geog & Earth Sci Charlotte NC 28223 USA Univ North Carolina Charlotte Project Mosa Charlotte NC 28223 USA

As a typical form of geographical phenomena, spatial flow events have been widely studied in contexts like migration, daily commuting, and information exchange through telecommunication. Studying the spatial pattern of flow data serves to reveal essential information about the underlying process generating the phenomena. Most methods of global clustering pattern detection and local clusters detection analysis are focused on single-location spatial events or fail to preserve the integrity of spatial flow events. In this research we introduce a new spatial statistical approach of detecting clustering (clusters) of flow data that extends the classical local K-function, while maintaining the integrity of flow data. Through the appropriate measurement of spatial proximity relationships between entire flows, the new method successfully upgrades the classical hot spot detection method to the stage of "hot flow" detection. Several specific aspects of the method are discussed to provide evidence of its robustness and expandability, such as the multi-scale issue and relative importance control, using a real data set of vehicle theft and recovery location pairs in Charlotte, NC.

关键词： INFORMATION sharing CLUSTER analysis (Statistics) SPATIAL analysis (Statistics) data analysis data flow computing

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Middleware and Metrology for the Pervasive Future

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IEEE PERVASIVE computing 2009年第3期8卷 74-83页

作者： Fillinger, Antoine Hamchi, Imad Degre, Stephane Diduch, Lukas L. Rose, Travis Fiscus, Jonathan Stanford, Vincent Nat. Inst. of Stand. & Technol. MD USA

Looks at the data and metrology tools developed by The National Institute of Standards and Technology for the research community, including common middleware for distributed sensor data acquisition and processing.

关键词： data acquisition data flow computing distributed sensors middleware open systems sensor fusion ubiquitous computing NIST data flow system collaborative development distributed sensor data acquisition interoperability metrology pattern recognition performance measurement pervasive system NDFS-II data flow data transport interoperability standards multimodal pervasive computing sensor networks user-sensitive interfaces Middleware Ubiquitous computing Performance metrics data transmission distributed sensors metrology Interoperability data Collection Methods NIST data flow Sensor fusion Pattern recognition open systems

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SYSTOLIC TEMPORAL ARITHMETIC - A NEW FORMALISM FOR SPECIFICATION AND VERIFICATION OF SYSTOLIC ARRAYS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1990年第8期9卷 804-820页

作者： LING, N BAYOUMI, MA UNIV SW LOUISIANA CTR ADV COMP STUDIESLAFAYETTELA 70504

A systolic temporal arithmetic (STA) formalism suitable for describing arithmetic operations in dynamic environments is introduced. It can be used for formal specification and verification of systolic arrays at the array architecture level. Besides providing value and operation abstraction from the lower level, it also exploits several features of systolic arrays, such as synchrony, regularity, repeatability, modularity, pipelinability, parallel processing ability, and spatial and temporal locality. STA provides constructs and verification techniques for simple, efficient, and effective systolic-array specification and verification. Verification techniques such as mathematical induction are suggested to exploit these systolic array features so as to speed up the process. STA overcomes several limitations of other existing specification and verification techniques and can be used with lower-level formalism for multilevel reasoning of systolic arrays. A brief description of this formalism and examples of how the formalism can be applied for formal specification and verification of two systolic arrays are discussed. Other applications of STA, such as simulations, fault diagnoses, and test generation for systolic arrays, are also suggested.< >

关键词： Arithmetic Systolic arrays Hardware Formal specifications Formal verification Parallel processing Testing data flow computing High performance computing Digital signal processing

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RANDOM MEASURE FIELDS AND THE INTEGRATION OF VISUAL INFORMATION

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IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS 1992年第4期22卷 705-716页

作者： MARROQUIN, JL Centro de Investigacion en Matematicas Guanajuato Mexico

The fundamental role that a class of layered probabilistic structures may play in the solution of certain complex approximation problems that appear in the integration of visual information is explained, specifically, those that involve the reconstruction of piecewise smooth functions using information from different channels. Specific models for these structures in the form of Markovian random fields of probability measures are developed, and practical algorithms are given for their computation, discussing their implementation both in terms of analog and digital networks (cellular automata). A simple application of this scheme to the reconstruction of piecewise smooth surfaces is discussed in detail. Its application to the solution of more complex problems that involve the interaction of several computational modules, such as the reconstruction of visible surfaces and automatic learning is outlined as well.

关键词： Image reconstruction Surface reconstruction Concrete Analog computers Computer networks data flow computing Optical computing Mechanical factors Layout Optical sensors

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Project verification and construction of superchip tests at the RTL level

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AUTOMATION AND REMOTE CONTROL 2013年第1期74卷 113-122页

作者： Zolotorevich, L. A. Belarusian State Univ Minsk BELARUS

Methods were proposed for project verification and directed design of the superchip tests represented in VHDL at the RTL level. The problem of test design and project verification was solved on the basis of the CNF-sa... 详细信息

关键词： ELECTRONIC systems -- Design & construction COMPUTER systems -- Verification RTL (Computer program language) VHDL (Computer hardware description language) data flow computing BOOLEAN functions (Mathematics)

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THE WHIRLWIND COMPUTER PROJECT

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 1990年第5期26卷 903-910页

作者： FORRESTER, JW EVERETT, RR MITRE CORP BEDFORDMA 01760

The authors describe how they led the development of the Whirlwind I (WWI) digital computer and its evolution into the SAGE (Semi-Automatic Ground Environment) air-defense system for North America. The project from 1945 through 1956, beginning at a time when no general-purpose, high-speed, electronic computer existed, was from the start dedicated to performance and reliability suitable for real-time control. After several shifts in objectives, Whirlwind became an experimental system for demonstrating that a digital computer could analyze the flow of radar data and generate control orders for fighter-plane interceptions of bombers. The resulting successor computers, the AN/FSQ-7, were installed in a network across the United States and Canada in the late 1950s. The SAGE System control centers were in operation about 25 years and demonstrated a 99.8% up-time reliability. In the Whirlwind Project, vacuum tube life was raised from 500 hours to 500000 hours, marginal checking allowed the automatic detection of aging and drifting of electronic components before they reached the point of failure, random-access magnetic-core storage was invented and developed to become the industry standard computer memory for more than two decades, synchronous parallel logic was used, computer-driven cathode-ray tube displays were used for the first time, light guns were used to permit an operator to identify displayed images to the computer for action, and multiple displays were time-shared between different operators.< >

关键词： Computer displays Concurrent computing Time sharing computer systems Computer network reliability Control systems Image storage North America High performance computing data flow computing Radar

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Morphling: A Reconfigurable Architecture for Tensor Computation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2022年第11期41卷 4733-4746页

作者： Lu, Liqiang Liang, Yun Peking Univ Ctr Energy Efficient Comp & Applicat Sch EECS Beijing 100871 Peoples R China

Tensor algebra plays a major role in various applications, including data analysis, machine learning, and hydrodynamics simulation. Different tensor algebra inherently varies in dimension, size, and computation, leading to different execution preference, including parallelization, data arrangement, and accumulation. Another critical aspect for tensor algebra is the involved tensors can be with varying mixes of dense and sparse representation. Such diversified applications are notoriously difficult to accelerate. Prior ASIC architectures do not meet the needs due to fixed dataflow and prior fine-grained fabrics (e.g., FPGAs) solutions offer limited performance and power improvement due to bit-level reconfigurable structure. In this article, we propose Morphling, a reconfigurable architecture that can flexibly handle both dense and sparse tensor computation. We first generalize a flexible execution model that decomposes tensor operations into three steps, including tensor vectorization, vector computation, and output reduction. The dense and sparse tensor computation share the same execution model, but differ in the vector computation step where the multiplications are conducted. Depending on the number of inputs and outputs that are linked together in the computation step, we define three parallel patterns, including many-to-one, one-to-many, and one-to-one, which correspond to different implementations for dense and sparse computation. Furthermore, to efficiently support sparse tensor, we design a tiled-BCSR format that enables high parallelism and balanced workload. At the architecture level, we propose a reconfigurable design to support the execution model. The hardware units can be reconfigured to support different datapath and enable different types of data reuse. We evaluate Morphling using various tensor operations and compare it with CPU, GPU, FPGA, and state-of-the-art ASIC designs. Overall, Morphling achieves 13.4X, 677.7X, 44.7X energy efficiency over Xili

关键词： Tensors Computer architecture Computational modeling Algebra Hardware Sparse matrices Field programmable gate arrays Accelerator architectures data flow computing reconfigurable architectures sparse matrices

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IBM POWER6 reliability

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 2007年第6期51卷 763-774页

作者： Mack, M. J. Sauer, W. M. Swaney, S. B. Mealey, B. G. IBM Syst & Technol Grp Austin TX 78758 USA IBM Syst & Technol Grp Poughkeepsie NY 12601 USA

This paper describes the state-of-the art reliability features of the IBM POWER6(TM) microprocessor. The POWER6 microprocessor includes a high degree of detection of soft and hard errors in both dataflow and control logic, as well as a feature-instruction retry recovery (IRR) - usually available only on mainframe systems. IRR provides full hardware error recovery of those registers that are defined by the instruction set architecture. This is accomplished by taking a checkpoint of the defined state for both of the core threads and recovering the machine state back to a known good point. To allow changing memory accessibility without using different page table entries, the POWER6 microprocessor implements virtual page class keys, a new architectural extension that enables the OS (operating system) to manage eight classes of memory with efficiently modifiable access authority for each class. With this feature, malfunctioning kernel extensions can be prevented from destroying OS data that may, in turn, bring an OS down.

关键词： RELIABILITY (Engineering) MICROPROCESSORS data flow computing OPERATING systems (Computers) COMPUTER software

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A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1999年第11期34卷 1608-1618页

作者： Suzuoki, M Kutaragi, K Hiroi, T Magoshi, K Okamoto, S Oka, M Ohba, A Yanamoto, Y Furuhashi, M Tanaka, M Yutaka, T Okada, T Nagamatsu, M Urakawa, Y Funyu, M Kunimatsu, A Goto, H Hashimoto, K Ide, N Murakami, H Ohtaguro, Y Aono, A Sony Comp Entertainment Inc Tokyo 1070052 Japan Toshiba Corp Semicond Co Kawasaki Kanagawa 210 Japan Toshiba Microelect Corp Kawasaki Kanagawa Japan

A 250-MHz microprocessor intended for home computer entertainment consists of a CPU core with 128-b multimedia extensions, two single-instruction, multiple-data (SIMD) very long instruction word (VLIW) vector processors containing ten floating-point multiplier accelerators and four floating-point dividers, an MPEG-2 decoder, a ten-channel direct memory access (DMA) controller, and other peripherals with 128-b internal buses on one die. The core is a two-way superscalar MIPS-compatible microprocessor with 16-kB scratch-pad RAM. Each vector processor is a five-way SIMD-VLIW architecture, which is tightly dedicated for specific applications about three-dimensional geometry calculation and physical simulation. A DMA controller connects between main memory and each professor's local memory to conceal memory access penalty. It contains 10.5 M transistors in 17 x 14.1 mm and dissipates 15 W at 1.8 V.

关键词： computer graphics data flow computing digital signal processing discrete cosine transform distributed memory system home computing image processing integrated circuit design multimedia systems multiprocessor interconnection real time systems

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