检索结果-内蒙古大学图书馆

Temporal partitioning and scheduling data flow graphs for reconfigurable computers

IEEE TRANSACTIONS ON COMPUTERS 1999年第6期48卷 579-590页

作者： Purna, KMG Bhatia, D Synopsys Inc Mountain View CA 94043 USA Univ Cincinnati Elect & Comp Engn & Comp Sci Dept Design Automat Lab Cincinnati OH 45521 USA

FPGA-based configurable computing machines are evolving rapidly. They offer the ability to deliver very high performance at a fraction of the cost when compared to supercomputers. The first generation of configurable computers (those with multiple FPGAs connected using a specific interconnect) used statically reconfigurable FPGAs. On these configurable computers, computations are performed by partitioning an entire task into spatially interconnected subtasks. Such configurable computers are used in logic emulation systems and for functional verification of hardware. In general, configurable computers provide the ability to reconfigure rapidly to any desired custom form. Hence, the available resources can be reused effectively to cut down the hardware costs and also improve the performance. In this paper, we introduce the concept of temporal partitioning to partition a task into temporally interconnected subtasks. Specifically, we present algorithms for temporal partitioning and scheduling data flow graphs for configurable computers. We are given a configurable computing unit (RPU) with a logic capacity of S-RPU and a computational task represented by an acyclic data now graph G = (V, E). Computations with logic area requirements that exceed S-RPU cannot be completely mapped on a configurable computer (using traditional spatial mapping techniques). However, a temporal partitioning of the data flow graph followed by proper scheduling can facilitate the configurable computer based execution. Temporal partitioning of the data flow graph is a k-way partitioning of G = (V, E) such that each partitioned segment will not exceed S-RPU in its logic requirement. Scheduling assigns an execution order to the partitioned segments so as to ensure proper execution. Thus, for each segment in {s(1), s(2), ..., s(k)}, scheduling assigns a unique ordering s(i) --> j, 1 less than or equal to i less than or equal to k, 1 less than or equal to j less than or equal to k, such that the comp

关键词： configurable computing field programmable gate arrays spatial partitioning temporal partitioning scheduling data flow graphs reconfigurable computers high performance computing

来源：评论

学校读者我要写书评

暂无评论

Intellectual property core protection of control data flow graphs using robust watermarking during behavioural synthesis based on user resource constraint and loop unrolling factor

引用

ELECTRONICS LETTERS 2016年第6期52卷 439-440页

作者： Sengupta, A. Bhadauria, S. Indian Inst Technol Indore Comp Sci & Engn Indore Madhya Pradesh India

A novel robust watermarking methodology for intellectual property core protection of control data flow graphs during behavioural synthesis based on user specified resource constraints and loop unrolling factor is proposed. The proposed methodology incorporates robust multi-variable signature encoding scheme for securing against typical attacks such as false claim of ownership and tampering. Some of the features of the watermarking include greater robustness, lower embedding cost, lower storage overhead, fault tolerance and faster encoding/decoding. Experimental results suggest that the watermarked solution generated by the proposed approach produces lower embedding cost than previous approaches, as well as is more secured due to its multi-variable signature encoding rules.

关键词： data flow graphs watermarking digital signatures microprocessor chips encoding decoding intellectual property core protection control data flow graphs behavioural synthesis user resource constraint loop unrolling factor robust watermarking methodology robust multivariable signature encoding scheme attack security false ownership claim attack tampering attack embedding cost storage overhead fault tolerance decoding scheme

来源：评论

学校读者我要写书评

暂无评论

data flow graphs granularity for overhead reduction within a PE in multiprocessor systems

Data flow graphs granularity for overhead reduction within a...

引用

1993 International Conference on Application Specific Array Processors, ASAP 1993

作者： Coli, M. Palazzari, P. Dipartimnto di Ingegneria Elettronica Universita La Sapienza Via Eudossiana 18 Roma00184 Italy

ISBN: (纸本)0818634928

The authors propose a method to implement Acyclic data flow graphs (ADFG) in any general purpose multiprocessor system supporting a CSP type language. The granularity of ADFG nodes is discussed During ADFG analysis the authors use fine granularity to exploit all the parallelism inherent in the problem. When the graph G has been allocated, it is divided into P subgraphs Gk (P is the number of the processors in the network);each of them is assigned to a processor Pk. Gk still presents some parallelism which cannot be usefully exploited and which implies a certain amount of overhead during Gk execution;the authors reduce this overhead by executing a post allocation analysis which increases the granularity of Gk nodes. In order to evaluate GTP performances the Overhead Reduction Ratio (ORR) is introduced. ORR is computed by using the results of several executions of GTP on randomly generated ADFG;the presented tests show the effectiveness of GTP. © 1993 IEEE.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Exploration of k_c-cycle transient fault-secured datapath and loop unrolling factor for control data flow graphs during high-level synthesis

引用

ELECTRONICS LETTERS 2015年第7期51卷 562-563页

作者： Sengupta, A. Indian Inst Technol Indore Madhya Pradesh India

Simultaneous design space exploration (DSE) of k(c)-cycle transient fault-secured datapath and loop unrolling factor (UF) for control data flow graphs (CDFGs) during high-level synthesis is an unsolved problem in the literature. The aforementioned problems are solved with the following specific contributions: (i) a novel DSE methodology that explores an optimal combination of transient fault-secured datapath configuration and loop UF using particle swarm optimisation for CDFG, and (ii) the novel k(c)-cycle fault secured algorithm. Finally, the proposed approach when tested on standard benchmarks yielded an optimal solution which minimises the fitness function and satisfies user constraints, as well as achieving significantly reduced cost of the final solution when compared with a recent fault-secured approach.

关键词： high level synthesis control data flow graphs simultaneous design space exploration Electronic engineering computing Combinatorial mathematics loop unrolling factor fitness function Computer-aided circuit analysis and design CDFGs kc-cycle transient fault-secured datapath configuration HLS particle swarm optimisation UF high-level synthesis DSE methodology PSO data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Modeling and Analysis of data flow graphs Using the Digraph Real-Time Task Model 21st

Modeling and Analysis of Data Flow Graphs Using the Digraph ...

引用

21st Ada-Europe International Conference on Reliable Software Technologies (Ada-Europe)

作者： Mohaqeqi, Morteza Abdullah, Jakaria Yi, Wang Uppsala Univ Uppsala Sweden

ISBN: (纸本)9783319390833;9783319390826

data flow graphs are widely used for modeling and analysis of real-time streaming applications in which having a predictable and reliable implementation is an essential requirement. In this paper, we consider scheduling a set of data flow graphs such that liveness and boundedness properties are guaranteed, which leads to a predictable and correct behavior of the application. A formal translation method is proposed to map a given set of data flow graphs to a set of graph-based real-time tasks. Additionally, sufficient conditions are derived under which the obtained task set provides a semantically correct implementation of the given data flow graphs. It is shown that the proposed approach provides a higher level of design flexibility compared to the existing methods which use a simpler, i.e. periodic, task model.

关键词： data flow graphs Real-time task models Buffer boundedness Schedulability analysis

来源：评论

学校读者我要写书评

暂无评论

Modeling Pipelined Application with Synchronous data flow graphs

Modeling Pipelined Application with Synchronous Data Flow Gr...

引用

13th International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Lattuada, Marco Ferrandi, Fabrizio Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20133 Milan Italy

ISBN: (纸本)9781479901036

Streaming applications can efficiently exploit multiprocessors architectures by means of pipelined parallelism, but designing this type of applications can be an hard task. Different subproblems have indeed to be solved: partitioning, mapping, scheduling and pipeline stage assignment. For this reason, high level abstraction models are adopted during design flow since they simplify this process by hiding most of the architectural details. Synchronous data flow (SDF) graphs, widely adopted to describe streaming applications, naturally model only their partitioning, so they usually have to be integrated with other types of representations. In this paper Pipelined Application Modeling (PAM), a methodology to create a Synchronous data flow graph describing all the aspects of a pipelined application, is presented. The methodology starts from the SDF graph describing the partitioning of the application and enriches it with new actors and channels detailing the mapping, the scheduling and the pipeline stage assignment of the considered solution. The obtained SDF graph, describing all the aspects of the solution in a formal and compact way, facilitates the evaluation of different solutions during design space exploration.

关键词： data flow graphs multiprocessing systems pipeline processing

来源：评论

学校读者我要写书评

暂无评论

Batchy: Batch-scheduling data flow graphs with Service-level Objectives 17

Batchy: Batch-scheduling Data Flow Graphs with Service-level...

引用

17th USENIX Symposium on Networked Systems Design and Implementation (NSDI)

作者： Levai, Tamas Nemeth, Felician Raghavan, Barath Retvari, Gabor Budapest Univ Technol & Econ Budapest Hungary Univ Southern Calif Los Angeles CA 90007 USA MTA BME Informat Syst Res Grp Budapest Hungary Ericsson Res Budapest Hungary

ISBN: (纸本)9781939133137

data flow graphs are a popular program representation in machine learning, big data analytics, signal processing, and, increasingly, networking, where graph nodes correspond to processing primitives and graph edges describe control flow. To improve CPU cache locality and exploit data-level parallelism, nodes usually process data in batches. Unfortunately, as batches are split across dozens or hundreds of parallel processing pathways through the graph they tend to fragment into many small chunks, leading to a loss of batch efficiency. We present Batchy, a scheduler for run-to-completion packet processing engines, which uses controlled queuing to efficiently reconstruct fragmented batches in accordance with strict service-level objectives (SLOs). Batchy comprises a runtime profiler to quantify batch-processing gain on different processing functions, an analytical model to fine-tune queue backlogs, a new queuing abstraction to realize this model in run-to-completion execution, and a one-step receding horizon controller that adjusts backlogs across the pipeline. We present extensive experiments on five networking use cases taken from an official 5G benchmark suite to show that Batchy provides 2-3x the performance of prior work while accurately satisfying delay SLOs.

关键词： data flow graphs

来源：评论

学校读者我要写书评

暂无评论

Latency-constrained Binding of data flow graphs to Energy Conscious GALS-based MPSoCs

Latency-constrained Binding of Data Flow Graphs to Energy Co...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Ambrose, Jude Angelo Nawinne, Isuru Parameswaran, Sri Univ New S Wales Sch Comp Sci & Engn Kensington NSW 2032 Australia

ISBN: (纸本)9781467357623;9781467357609

Mapping tasks to cores in an Multiprocessor Systemon-Chip (MPSoC) to meet constraints is widely investigated. Thus far the data flow graphs used for binding have been limited to acyclic graphs or have been single rate. In this paper we generalize the approach by allowing DFGs to be cyclic and multi rate. We further improve energy consumption by setting frequency per core in a Globally Asynchronous and Locally Synchronous (GALS) architecture (by the distribution of slack). A design flow is proposed with these two approaches to form a latency constrained and energy efficient binding. A generalized solution is proposed, compared to state-of-the-art, using improvements in formulation, data structures and heuristics. Eight benchmarks are experimented upon for mesh and pipeline architectures. Our heuristics achieve significant simulation speedup compared to the state-of-the-art and provide a solution which is 2.5% lower (26% worst case) than the optimal, but the solution is obtained 40x quicker (average case). Such a speedup allows us to rapidly explore a large design space.

关键词： data flow graphs integrated circuit design multiprocessing systems system-on-chip

来源：评论

学校读者我要写书评

暂无评论

Using Stream Rewriting for Mapping and Scheduling data flow graphs onto Many-Core Architectures

Using Stream Rewriting for Mapping and Scheduling Data Flow ...

引用

47th Asilomar Conference on Signals, Systems, and Computers

作者： Haubelt, Christian Ludwig, Florian Middendorf, Lars Zebelein, Christian Univ Rostock D-18055 Rostock Germany

ISBN: (纸本)9781479923908

dataflow graphs, consisting of concurrent actors connected by communication channels, are widely used to model multimedia applications. As dataflow graphs explicitly expose the parallelism contained in the application, they yield well to synthesis for many-core architectures. However, in case of varying and unpredictable workloads, a static mapping of actors to computing resources is often infeasible, but a dynamic approach becomes challenging due to the numerous amount of actors. Our concept of stream-rewriting represents a novel execution semantics for dataflow graphs on many-core architectures, which allows for a completely dynamic binding of actors instances to processing units. In addition, we present a distributed scheduling mechanism, global resource sharing and lightweight lock-free synchronization based on pattern matching. Also, an optimized architecture for stream-rewriting is prototyped and evaluated.

关键词： core construction data flow graphs actor ARCHITECTURE data flow MAPPING(MATHEMATICAL) mapping Communication channels Resource sharing parallelism

来源：评论

学校读者我要写书评

暂无评论

Analyzing preemptive Fixed Priority Scheduling of data flow graphs 12

Analyzing preemptive Fixed Priority Scheduling of Data Flow ...

引用

12th IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia)

作者： Lele, Alok Moreira, Orlando Bastos, Joao Almeida, Ricardo Pedreiras, Paulo van Berkel, Kees Eindhoven Univ Eindhoven Netherlands Ericsson BV Eindhoven Eindhoven Netherlands Univ Aveiro Aveiro Portugal

ISBN: (纸本)9781479963072

data flow graphs can conveniently model embedded streaming applications (ESAs) that are typically implemented as networks of concurrent tasks having an iterative pipelined execution, where the activation of each task may be conditioned by intra-and inter-iteration data dependencies. We propose a novel analysis approach for preemptive Fixed Priority Scheduling (FPS) of multiple ESAs assuming a fixed mapping of tasks onto the processors of the underlying Heterogeneous Multi-Processor System-on-Chip (HMPSoC). The tasks of an ESA are event activated, have varying execution times, and participate in cyclic dependency chains such that they may not have an activation pattern that can be depicted using traditional periodic / sporadic event models. Instead we propose to characterize the data flow graphs of ESAs to upper bound the load they impose on a processor and use it to compute the worst-case response time of an actor executing on that processor at a lower priority. We show that ours is a generic approach for analyzing FPS of data flow graphs. We also propose a refinement of our technique for graphs with a dominant periodic source. We demonstrate our improvement over the state-of-the-art FPS analysis for data flow in our experiments.

关键词： data flow graphs multiprocessing systems scheduling system-on-chip FPS HMPSoC activation pattern cyclic dependency chains embedded streaming applications heterogeneous multiprocessor system-on-chip iterative pipelined execution multiple ESA periodic event models preemptive fixed priority scheduling sporadic event models tasks fixed mapping worst-case response time Analytical models data models Interference Load modeling Program processors Schedules Time factors data flow graphs FES gene Program processors Multiprocessing systems system-on-chip data models Load modeling Time Factors ANALYSIS MODELS PROCESSOR

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：