Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these d...
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Since their appearance, programmable logic controllers (PLCs) are massively and predominantly used as the central controller in automation systems. Unfortunately, due to the poor performance of the majority of these devices, the typical role of PLCs in automation systems becomes restricted to a simple controller, since applications with more sophisticated computational requirements tend to be handled by external processing units along with the PLCs. To solve this issue, this work improves novel architecture proposals based on data flow machines, circuit simulation theory, and the memoization technique to achieve a performance boost based on the scan time reduction. Along with the architectural improvements, this paper evaluates the impact of different execution units' types and quantities in a cycle-accurate simulator (CAS) that was specially developed to simulate the PLC cores. Furthermore, in order to perform a robust and complete evaluation, the silicon areas of the simulated architectures are calculated using the McPAT framework to establish the performance/area relationship of the simulated cores. Evaluation results show best scan time reductions of up to 68% for cores with single execution units and up to 89% for cores with multiple execution units, as well as a best-case of 50% scan time reduction with an acceptable impact on the silicon area. Lastly, the evaluation of the results of the proposed improved cores with multiple execution units shows that they outperform the theoretical performance limit of multiple execution units based on Amdahl's law up to 4 execution units. (C) 2020 Elsevier B.V. All rights reserved.
Programmable logic controllers (PLCs) are massively used as the central processing control units in industrial automation solutions. Unfortunately, the lack of performance of these controllers requires coupling specif...
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Programmable logic controllers (PLCs) are massively used as the central processing control units in industrial automation solutions. Unfortunately, the lack of performance of these controllers requires coupling specific drivers to the PLCs to enable deterministic response in time-sensitive real-time applications, thus reducing the importance of the PLCs in the entire automation systems. Current solutions do not focus on PLC performance, and it is, therefore, safer to use the design pattern with these specific drivers when required. This situation does not give PLC users of those solutions full control of the provided automation and, consequently, it increases the price of the entire system, as well as the need for spare parts. To put PLCs back as central processing units of industrial automation technology and to reduce the need for specific drivers, this work proposes a novel architecture with enhanced improvements based mainly on the concepts of dataflow computation and memoization technique to boost PLC performance. Evaluations made on the proposed design demonstrate a reduction of 95% in the proposed architecture's scan time and show significant performance boost even in small-scale, didactic and straightforward examples. Moreover, the experimental evaluations also have demonstrated the potential for continued performance improvement with the increase of the program size.
Task-based programming Task-based programming models such as OpenMP, Intel TBB and OmpSs are widely used to extract high level of parallelism of applications executed on multi-core and manycore platforms. These progra...
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ISBN:
(纸本)9781538632505
Task-based programming Task-based programming models such as OpenMP, Intel TBB and OmpSs are widely used to extract high level of parallelism of applications executed on multi-core and manycore platforms. These programming models allow applications to be expressed as a set of tasks with dependences to drive their execution at runtime. While managing these dependences for task with coarse granularity proves to be highly beneficial, it introduces noticeable overheads when targeting fine-grained tasks, diminishing the potential speedups or even introducing performance losses. To overcome this drawback, we propose a hardware/software co-design Picos that manages inter-task dependences efficiently. In this paper we describe the main ideas of our proposal and a prototype implementation. This prototype is integrated with a parallel task based programming model and evaluated with real executions in Linux embedded system with two ARM Cortex-A9 and a FPGA. When compared with a software runtime, our solution results in more than 1.8x speedup and 40% of energy savings with only 2 threads.
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