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data parallelization Algorithms for the Direct Simulation Monte Carlo Method for Rarefied Gas Flows on the Basis of OpenMP Technology

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COMPUTATIONAL MATHEMATICS AND MATHEMATICAL PHYSICS 2023年第12期63卷 2275-2296页

作者： Bykov, N. Yu. Fyodorov, S. A. Russian Acad Sci Fed Res Ctr Comp Sci & Control Moscow 119333 Russia Peter Great St Petersburg Polytech Univ St Petersburg 195251 Russia

A data parallelization algorithm for the direct simulation Monte Carlo method for rarefied gas flows is considered. The scaling of performance of the main algorithm procedures are analyzed. Satisfactory performance scaling of the parallel particle indexing procedure is shown, and an algorithm for speeding up the operation of this procedure is proposed. Using examples of solving problems of free flow and flow around a cone for a 28-core node with shared memory, an acceptable speedup of the entire algorithm was obtained. The efficiency of the data parallelization algorithm and the computational domain decomposition algorithm for free flow is compared. Using the developed parallel code, a study of the supersonic rarefied flow around a cone is carried out.

关键词： direct simulation Monte Carlo method parallel algorithms data parallelization OpenMP rarefied gas flow around cone

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Accelerating Recurrent Neural Network Training using Sequence Bucketing and Multi-GPU data parallelization 1

Accelerating Recurrent Neural Network Training using Sequenc...

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1st IEEE International Conference on data Stream Mining and Processing (DSMP)

作者： Khomenko, Viacheslav Shyshkov, Oleg Radyvonenko, Olga Bokhan, Kostiantyn Samsung R& Inst Ukraine SRK 57 Lva Tolstogo Str UA-01032 Kiev Ukraine

ISBN: (纸本)9781509037360

An efficient algorithm for recurrent neural network training is presented. The approach increases the training speed for tasks where a length of the input sequence may vary significantly. The proposed approach is based on the optimal batch bucketing by input sequence length and data parallelization on multiple graphical processing units. The baseline training performance without sequence bucketing is compared with the proposed solution for a different number of buckets. An example is given for the online handwriting recognition task using an LSTM recurrent neural network. The evaluation is performed in terms of the wall clock time, number of epochs, and validation loss value.

关键词： recurrent neural network mini-batch sequence bucketing data parallelization LSTM GPU

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Accelerating BWA Aligner Using Multistage data parallelization on Multicore and Manycore Architectures

Accelerating BWA Aligner Using Multistage Data Parallelizati...

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16th Annual International Conference on Computational Science (ICCS)

作者： Chen, Shaolong Senar, Miquel A. Univ Autonoma Barcelona Dept Comp Architecture & Operating Syst Barcelona Spain

Nowadays, rapid progress in next generation sequencing (NGS) technologies has drastically decreased the cost and time required to obtain genome sequences. A series of powerful computing accelerators, such as GPUs and Xeon Phi MIC, are becoming a common platform to reduce the computational cost of the most demanding processes when genomic data is analyzed. GPU has received more attention at literature so far. However, Xeon Phi constitutes a very attractive approach to improve performance because applications don't need to be rewritten in a different programming language specifically oriented to it. Sequence alignment is a fundamental step in any variant analysis study and there are many tools that cope with this problem. We have selected BWA, one of the most popular sequence aligner, and studied different data management strategies to improve its execution time on hybrid systems made of multicore CPUs and Xeon Phi accelerators. Our main contributions are focused on designing new strategies that combine data splitting and index replication in order to achieve a better balance in the use of system memory and reduce latency penalties. Our experimental results show significant speed-up improvements when such strategies are executed in our hybrid platform, taking advantage of the combined computing power of a standard multicore CPU and a Xeon Phi accelerator.

关键词： Xeon Phi Sequence alignment data parallelization Multicore processors Manycore processors

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Accelerating BWA Aligner Using Multistage data parallelization on Multicore and Manycore Architectures

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Procedia Computer Science 2016年 80卷 2438-2442页

作者： Shaolong Chen Miquel A. Senar Department of Computer Architecture & Operating System Universitat Autònoma de Barcelona Spain

Nowadays, rapid progress in next generation sequencing (NGS) technologies has drastically decreased the cost and time required to obtain genome sequences. A series of powerful computing accelerators, such as GPUs and Xeon Phi MIC, are becoming a common platform to reduce the computational cost of the most demanding processes when genomic data is analyzed. GPU has received more attention at literature so far. However, Xeon Phi constitutes a very attractive approach to improve performance because applications don’t need to be rewritten in a different programming language specifically oriented to it. Sequence alignment is a fundamental step in any variant analysis study and there are many tools that cope with this problem. We have selected BWA, one of the most popular sequence aligner, and studied different data management strategies to improve its execution time on hybrid systems made of multicore CPUs and Xeon Phi accelerators. Our main contributions are focused on designing new strategies that combine data splitting and index replication in order to achieve a better balance in the use of system memory and reduce latency penalties. Our experimental results show significant speed-up improvements when such strategies are executed in our hybrid platform, taking advantage of the combined computing power of a standard multicore CPU and a Xeon Phi accelerator.

关键词： Xeon Phi Sequence alignment data parallelization Multicore processors Manycore processors

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FPGA-based Fast Image Warping with data-parallelization Schemes

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IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2008年第4期54卷 2053-2059页

作者： Oh, Sungchan Kim, Gyeonghwan Sogang Univ Dept Elect Engn Seoul South Korea

In this paper, we present an FPGA-based fast image warping method by applying data parallelization schemes. The parallelization of accesses to pixels relieves not only latency problem of the warping, but also bandwidth requirements of off-chip memory. The LUT data parallelization scheme efficiently replaces parallel arithmetic operations with neither of increased memory size for LUT entries nor clock frequency. Two implementations with different characteristics prove the effectiveness and efficiency of the proposed method.

关键词： data parallelization image transformation image warping lookup tables FPGA

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RAPIDSCORER: Fast Tree Ensemble Evaluation by Maximizing Compactness in data Level parallelization 18

RAPIDSCORER: Fast Tree Ensemble Evaluation by Maximizing Com...

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24th ACM SIGKDD Conference on Knowledge Discovery and data Mining (KDD)

作者： Ye, Ting Zhou, Hucheng Zou, Will Y. Gao, Bin Zhang, Ruofei Microsoft Vancouver BC Canada Alibaba Grp Hangzhou Zhejiang Peoples R China Microsoft Sunnyvale CA USA Microsoft Redmond WA USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781450355520

Relevance ranking models based on additive ensembles of regression trees have shown quite good effectiveness in web search engines. In the era of big data, tree ensemble models grow large in both tree depth and ensemble size to provide even better search relevance and user experience. However, the computational cost for their scoring process is high, such that it becomes a challenging issue to apply the big tree ensemble models in a search engine which needs to answer thousands of queries per second. Although several works have been proposed to improve the scoring process, the challenge is still great especially when the model size grows large. In this paper, we present RAPIDSCORER, a novel framework for speeding up the scoring process of industry-scale tree ensemble models, without hurting the quality of scoring results. RAPIDSCORER introduces a modified run length encoding called epitome to the bitvector representation of the tree nodes. Epitome can greatly reduce the computation cost to traverse the tree ensemble, and work with several other proposed strategies to maximize the compactness of data units in memory. The achieved compactness makes it possible to fully utilize data parallelization to improve model scalability. Experiments on two web search benchmarks show that, RAPIDSCORER achieves significant speed-up over the state-of-the-art methods: V-QUICKSCORER, ranging from 1.3x to 3.5x;QUICKSCORER, ranging from 2.1x to 25.0x;VPRED, ranging from 2.3x to 18.3x;and XGBOOST, ranging from 2.6x to 42.5x.

关键词： vpred data parallelization run length encoding quickscorer simd tree ensemble traversal xgboost industry-scale models efficiency

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A Hybrid parallelization Approach for Distributed and Scalable Deep Learning

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IEEE ACCESS 2022年 10卷 77950-77961页

作者： Akintoye, Samson B. Han, Liangxiu Zhang, Xin Chen, Haoming Zhang, Daoqiang Manchester Metropolitan Univ Dept Comp & Math Manchester M15 6BH Lancs England Univ Sheffield Dept Comp Sci Sheffield S10 2TN S Yorkshire England Nanjing Univ Aeronaut & Astronaut Coll Comp Sci & Technol Nanjing 210016 Peoples R China

Recently, Deep Neural Networks (DNNs) have recorded significant success in handling medical and other complex classification tasks. However, as the sizes of DNN models and the available datasets increase, the training process becomes more complex and computationally intensive, usually taking longer to complete. In this work, we have proposed a generic full end-to-end hybrid parallelization approach combining model and data parallelism for efficiently distributed and scalable training of DNN models. We have also proposed a Genetic Algorithm Based Heuristic Resources Allocation (GABRA) mechanism for optimal distribution of partitions on the available GPUs for computing performance optimization. We have applied our proposed approach to a real use case based on 3D Residual Attention Deep Neural Network (3D-ResAttNet) for efficient Alzheimer Disease (AD) diagnosis on multiple GPUs and compared with the existing state-of-the-art parallel methods. The experimental evaluation shows that our proposed approach is 20% averagely better than existing parallel methods in terms of training time and achieves almost linear speedup with little or no differences in accuracy performance when compared with the existing non-parallel DNN models.

关键词： Computational modeling data models Training Resource management Genetic algorithms Computer architecture Neural networks Deep learning genetic algorithm data parallelization model parallelization

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Predictable Low-Latency Event Detection With Parallel Complex Event Processing

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IEEE INTERNET OF THINGS JOURNAL 2015年第4期2卷 274-286页

作者： Mayer, Ruben Koldehofe, Boris Rothermel, Kurt Univ Stuttgart Inst Parallel & Distributed Syst D-70569 Stuttgart Germany Tech Univ Darmstadt Multimedia Commun Lab D-64283 Darmstadt Germany

The tremendous number of sensors and smart objects being deployed in the Internet of Things (IoT) pose the potential for IT systems to detect and react to live-situations. For using this hidden potential, complex event processing (CEP) systems offer means to efficiently detect event patterns (complex events) in the sensor streams and therefore, help in realizing a "distributed intelligence" in the IoT. With the increasing number of data sources and the increasing volume at which data is produced, parallelization of event detection is crucial to limit the time events need to be buffered before they actually can be processed. In this paper, we propose a pattern-sensitive partitioning model for data streams that is capable of achieving a high degree of parallelism in detecting event patterns, which formerly could only consistently be detected in a sequential manner or at a low parallelization degree. Moreover, we propose methods to dynamically adapt the parallelization degree to limit the buffering imposed on event detection in the presence of dynamic changes to the workload. Extensive evaluations of the system behavior show that the proposed partitioning model allows for a high degree of parallelism and that the proposed adaptation methods are able to meet a buffering limit for event detection under high and dynamic workloads.

关键词： Complex event processing (CEP) data parallelization quality of service self-adaptation stream processing

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Big data Applications Using Workflows for data Parallel Computing

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COMPUTING IN SCIENCE & ENGINEERING 2014年第4期16卷 11-21页

作者： Wang, Jianwu Crawl, Daniel Altintas, Ilkay Li, Weizhong Univ Calif San Diego Workflows Data Sci WorDS Ctr Excellence San Diego CA 92103 USA Univ Calif San Diego San Diego Supercomp Ctr San Diego CA 92103 USA Univ Calif San Diego Workflows Data Sci Ctr Excellence San Diego Supercomp Ctr San Diego CA 92103 USA Univ Calif San Diego Ctr Res Biol Syst San Diego CA 92103 USA

In the Big data era, workflow systems must embrace data parallel computing techniques for efficient data analysis and analytics. Here, an easy-to-use, scalable approach is presented to build and execute Big data applications using actor-oriented modeling in data parallel computing. Two bioinformatics use cases for next-generation sequencing data analysis demonstrate the approach's feasibility.

关键词： Big data workflow actor-oriented programming bioinformatics application data parallelization scientific computing scientific programming

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Optimizing two-dimensional DMA transfers for scratchpad Based MPSoCs platforms

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MICROPROCESSORS AND MICROSYSTEMS 2013年第8期37卷 848-857页

作者： Saidi, Selma Tendulkar, Pranav Lepley, Thierry Maler, Oded Univ Grenoble CNRS VERIMAG Lab Gieres France STMicroelectronics Grenoble France

Reducing the effects of off-chip memory access latency is a key factor in exploiting efficiently embedded multi-core platforms. We consider architectures that admit a multi-core computation fabric, having its own fast and small memory to which the data blocks to be processed are fetched from external memory using a DMA (direct memory access) engine, employing a double- or multiple-buffering scheme to avoid processor idling. In this paper we focus on application programs that process two-dimensional data arrays and we determine automatically the size and shape of the portions of the data array which are subject to a single DMA call, based on hardware and applications parameters. When the computation on different array elements are completely independent, the asymmetry of memory structure leads always to prefer one-dimensional horizontal pieces of memory, while when the computation of a data element shares some data with its neighbors, there is a pressure for more "square" shapes to reduce the amount of redundant data transfers. We provide an analytic model for this optimization problem and validate our results by running a mean filter application on the au. simulator. (C) 2013 Elsevier B.V. All rights reserved.

关键词： data parallelization Direct memory access (DMA) Double buffering Cell processor MPSoCs

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