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Exploring Synchronous Page Fault Handling

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2022年第11期41卷 3791-3802页

作者： Chen, Yin-Chiuan Wu, Chun-Feng Chang, Yuan-Hao Kuo, Tei-Wei Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei 106 Taiwan Natl Yang Ming Chiao Tung Univ Dept Comp Sci Hsinchu 300 Taiwan Harvard Univ Dept Comp Sci Cambridge MA 02138 USA Acad Sinica Inst Informat Sci Taipei 115 Taiwan City Univ Hong Kong Coll Engn Hong Kong Peoples R China

The advance of nonvolatile memory in storage technology has presented challenges in redefining the ways in handling the main memory and the storage. This work is motivated by the strong demands in effective handling of page faults over ultralow-latency storage devices. In particular, we propose synchronous and asynchronous prefetching strategies to satisfy process executions with different memory demands in supporting of synchronous page fault handling. An adaptive CPU scheduling strategy is also proposed to cope with the needs of processes in maintaining their working sets in the main memory. Six representative benchmarks and applications were evaluated. It was shown that our strategy can effectively save 12.33% of the total execution time and reduce 13.33% of page faults, compared to the conventional demand paging strategy with nearly no sacrificing of process fairness.

关键词： Circuit faults prefetching Switches Memory management Performance evaluation Central Processing Unit Time factors Context switch data prefetching killer microsecond page faults process scheduler synchronous I O completion designs ultralow-latency (ULL) devices

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Boosting data throughput for sequence database similarity searches on FPGAs using an adaptive buffering scheme

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PARALLEL COMPUTING 2009年第1期35卷 1-11页

作者： Meng, X. Chaudhary, V. Texas A&M Univ Supercomp Facil College Stn TX 77843 USA SUNY Buffalo NYS Ctr Excellence Bioinformat & Life Sci Dept Comp Sci & Engn Buffalo NY 14260 USA

Searching on DNA and protein databases using sequence comparison algorithms has become one of the most powerful techniques to better understand the functionality of particular biological sequences. However, the requirements to process the biological data exceed the ability of general-purpose processors. FPGAs (Field Programmable Gate Arrays) connected to server processors have been used to accelerate similarity searches. However, reconfigurable computing platforms have utilized an external I/O bus as the communications channel, limiting the communication speed between the host processor and the FPGA. This communication bottleneck often offsets the application speedup enabled by FPGAs. In this paper we present an adaptive data prefetching scheme to avoid reconfigurable processing coprocessor stalls due to data unavailability through profiling methodologies and quantitative analysis. Experimental results on various query sequences show that the proposed scheme can effectively eliminate a major portion of the data access penalty, increase throughput of the FPGA implementation by up to 42%, and achieve a speedup of 110 for affine gap penalties over a standard PC implementation. Published by Elsevier B.V.

关键词： FPGA PCI Direct memory access Smith-Waterman algorithm data prefetching

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Algorithm-level Feedback-controlled Adaptive data prefetcher: Accelerating data access for high-performance processors

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PARALLEL COMPUTING 2012年第10-11期38卷 533-551页

作者： Chen, Yong Zhu, Huaiyu Jin, Hui Sun, Xian-He Texas Tech Univ Dept Comp Sci Lubbock TX 79409 USA Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA IIT Dept Comp Sci Chicago IL 60616 USA

The rapid advance of processor architectures such as the emerged multicore architectures and the substantially increased computing capability on chip have put more pressure on the sluggish memory systems than ever. In the meantime, many applications become more and more data intensive. data-access delay, not the processor speed, becomes the leading performance bottleneck of high-performance computing. data prefetching is an effective solution to accelerating applications' data access and bridging the growing gap between computing speed and data-access speed. Existing works of prefetching, however, are very conservative in general, due to the computing power consumption concern of the past. They suffer low effectiveness especially when applications' access pattern changes. In this study, we propose an Algorithm-level Feedback-controlled Adaptive (AFA) data prefetcher to address these issues. The AFA prefetcher is based on the data-Access History Cache, a hardware structure that is specifically designed for data access acceleration. It provides an algorithm-level adaptation and is capable of dynamically adapting to appropriate prefetching algorithms at runtime. We have conducted extensive simulation testing with the SimpleScalar simulator to validate the design and to analyze the performance gain. The simulation results show that the AFA prefetcher is effective and achieves considerable IPC (Instructions Per Cycle) improvement for 21 representative SPEC-CPU benchmarks. (C) 2012 Elsevier B.V. All rights reserved.

关键词： data prefetching Adaptive prefetching data access acceleration Application accelerator High-performance processors Memory hierarchy Memory wall

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Speculative pre-execution assisted by compiler (SPEAR)

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JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING 2006年第8期66卷 1076-1089页

作者： Ro, Won W. Gaudiot, Jean-Luc Univ Calif Irvine Henry Samueli Sch Engn Dept Elect Engn & Comp Sci Irvine CA 92697 USA Calif State Univ Northridge Dept Elect & Comp Engn Northridge CA 91330 USA

Speculative pre-execution achieves efficient data prefetching by running additional prefetching threads on spare hardware contexts. Various implementations for speculative pre-execution have been proposed, including compiler-based static approaches and hardware-based dynamic approaches. A static approach defines the p-thread at compile time and executes it as a stand-alone running thread. Therefore, it cannot efficiently take dynamic events into account and requires a higher fetch bandwidth. Conversely, a hardware approach is, by essence, able to dynamically make use of run-time information. However, it requires more complex hardware and also lacks global information on data and control flow. This paper proposes Speculative Pre-Execution Assisted by compileR (SPEAR), a pre-execution model which is a hybrid of the two approaches. It relies on a post-compiler to extract the p-thread code from program binaries and uses custom-designed hardware to execute the p-thread. (C) 2006 Elsevier Inc. All rights reserved.

关键词： data prefetching speculative pre-execution simultaneous multi-threading instruction-level parallelism

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PARS: A Pattern-Aware Spatial data Prefetcher Supporting Multiple Region Sizes

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第11期43卷 3638-3649页

作者： Lin, Yiquan Lin, Wenhai Xu, Jiexiong Chen, Yiquan Jin, Zhen Qin, Jingchang He, Jiahao Cai, Shishun Zhang, Yuzhong Wang, Zonghui Chen, Wenzhi Zhejiang Univ Coll Comp Sci & Technol Hangzhou 310027 Peoples R China Alibaba Grp Cloud Infrastruct Serv Hangzhou 310030 Peoples R China

Hardware data prefetching is a well-studied technique to bridge the processor-memory performance gap. Bit-pattern-based prefetchers are one of the most promising spatial data prefetchers that achieve substantial performance gains. In bit-pattern-based prefetchers, the region size is a crucial parameter, which denotes the memory size that can be recorded by a pattern or prefetched by a prediction. However, existing bit-pattern-based prefetchers only support one fixed region size. Our experiment shows that the fixed region size cannot meet the requirements for numerous applications and leads to suboptimal performance and high hardware overhead. In this article, we propose PARS, a pattern-aware spatial data prefetcher supporting multiple region sizes. The key idea of PARS is that it supports multiple region sizes, enabling it to simultaneously enhance application performance while reducing the hardware overhead. Moreover, PARS supports dynamically switching appropriate region sizes for different patterns through an adaptive RS-switching mechanism. We evaluated PARS on numerous workloads and results show that PARS provides an average performance improvement of 40.6% over a baseline with no data prefetchers and outperforms the two state-of-the-art prefetchers Bingo by 2.1% (up to 24.4%) and Pythia by 3.9% (up to 111.2%) in the single-core system. In the four-core system, PARS outperforms Bingo by 5.0% (up to 66.0%) and Pythia by 5.4% (up to 177.9%).

关键词： Integrated circuits Bridges Design automation prefetching Switches Performance gain Spatial databases Hardware Cache data prefetching hardware prefetching microarchitecture

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Secondary cache enhancement using a novel tagged prefetching method

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MICROPROCESSORS AND MICROSYSTEMS 1999年第4期23卷 245-253页

作者： Ki, A Elect & Telecommun Res Inst Comp Syst Dept Comp & Software Technol Lab Taejon 305350 South Korea

data prefetching, which issues data fetch requests prior to actual use, is an effective technique to reduce the effects of memory access latency. In this paper, we propose an implementation of tagged data prefetching that needs no cache modification and fairly simple hardware. Using a program driven simulation of scientific applications in the context of shared-memory multiprocessors, it is shown that the proposed method can result in performance equal to or better than that of conventional tagged prefetching. (C) 1999 Elsevier Science B.V. All rights reserved.

关键词： data prefetching tagged prefetching memory latency multiprocessors

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A decoupled predictor-directed stream prefetching architecture

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IEEE TRANSACTIONS ON COMPUTERS 2003年第3期52卷 260-276页

作者： Sair, S Sherwood, T Calder, B Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

An effective method for reducing the effect of load latency in modern processors is data prefetching. One form of hardware-based data prefetching, stream buffers, has been shown to be particularly effective due to its ability to detect data streams and run ahead of them, prefetching as it goes. Unfortunately, in the past, the applicability of streaming was limited to stride intensive code. In this paper, we propose Predictor-Directed Stream Buffers (PSB), which allows the stream buffer to follow a general address prediction stream instead of a fixed stride. A general address prediction stream complicates the allocation of both stream buffer and memory resources because the predictions generated will not be as reliable as prior sequential next-fine and stride-based stream buffer implementations. To address this, we examine using confidence-based techniques to guide the allocation and prioritization of stream buffers and their prefetch requests. Our results show, when using PSB on a benchmark suite heavy in pointer-based applications, that PSB provides a 23 percent speedup on average over the best previous stream buffer implementation, and an improvement of 75 percent over using no prefetching at all.

关键词： data prefetching stream buffers address prediction

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A performance study on bounteous transfer in multiprocessor sectored caches

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JOURNAL OF SUPERCOMPUTING 1997年第4期11卷 405-420页

作者： Liu, KC King, CT Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30043 Taiwan

In a sectored cache, a cache line is divided into several subblocks. Each subbIock is a basic coherence unit. In this way partial block invalidation can be done on the cache lines in order to eliminate false sharing on invalidate-based multiprocessors. Sectored caches often include a facility, called bounteous transfers, to supply extra subblocks after transferring the missed subblock on a read miss. Unfortunately, previous works on sectored caches concentrated mainly on solving the false sharing problem, while overlooked the prefetching effects of bounteous transfer. In this paper, we evaluate the performance impacts of bounteous transfer based on a MESI-based sectored cache. Three different types of bounteous transfer are evaluated: bounteous transfer with valid subblocks(BT-V), bounteous transfer with clean subblocks (BT-C). and bounteous transfer disabled (No-BT). We simulated the execution of typical benchmarks, FFT, LU, Radix, SOR, on the MESI-based sectored cache. Two metrics Lf-rate and R-rate are proposed to help observe the sharing granularities and coherence overhead. Evaluation results show that different benchmarks work better with different kinds of bounteous transfer and using bounteous transfer carelessly may result in performance degradation.

关键词： cache coherence multiprocessor sectored cache partial block invalidation data prefetching false sharing

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Exploring prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory database Lookups

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2020年第1期19卷 5-8页

作者： Cavus, Mustafa Shatnawi, Mohammed Sendag, Resit Uht, Augustus K. Univ Rhode Isl Dept Elect Comp & Biomed Engn Kingston RI 02881 USA

Lookup operations for in-memory databases are heavily memory-bound because they often rely on pointer-chasing linked data structure traversals. They are also branch heavy with branches that are hard-to-predict due to random key lookups. In this study, we show that although cache misses are the primary bottleneck for these applications, without a method for eliminating the branch mispredictions, only a small fraction of the performance benefit is achieved through prefetching. We propose the Node Tracker (NT), a novel programmable prefetcher/pre-execution unit that is highly effective in exploiting inter key-lookup parallelism to improve single-thread performance. We extend the NT with branch outcome streaming (BOS) to reduce branch mispredictions and show that NT with BOS can achieve an extra 3x speedup. Finally, we evaluated the NT as a pre-execution unit and show that we can further improve the performance in both single- and multi-threaded execution modes.

关键词： prefetching Task analysis Hardware Parallel processing Multicore processing databases data prefetching branch prediction pre-execution hardware acceleration key-value lookups

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Fast data Delivery for Many-Core Processors

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IEEE TRANSACTIONS ON COMPUTERS 2018年第10期67卷 1416-1429页

作者： Bakhshalipour, Mohammad Lotfi-Kamran, Pejman Mazloumi, Abbas Samandi, Farid Naderan-Tahan, Mahmood Modarressi, Mehdi Sarbazi-Azad, Hamid SUT Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Univ Tehran Tehran Iran Univ Calif Riverside Dept Comp Sci Riverside CA 92521 USA Shahid Chamran Univ Ahvaz SCU Dept Comp Engn Fac Engn Ahvaz Khuzestan Iran Univ Tehran Sch Elect & Comp Engn Tehran Iran SUT Dept Comp Engn Tehran Iran

Server workloads operate on large volumes of data. As a result, processors executing these workloads encounter frequent L1-D misses. In a many-core processor, an L1-D miss causes a request packet to be sent to an LLC slice and a response packet to be sent back to the L1-D, which results in high overhead. While prior work targeted response packets, this work focuses on accelerating the request packets. Unlike aggressive OoO cores, simpler cores used in many-core processors cannot hide the latency of L1-D request packets. We observe that LLC slices that serve L1-D misses are strongly temporally correlated. Taking advantage of this observation, we design a simple and accurate predictor. Upon the occurrence of an L1-D miss, the predictor identifies the LLC slice that will serve the next L1-D miss and a circuit will be set up for the upcoming miss request to accelerate its transmission. When the upcoming miss occurs, the resulting request can use the already established circuit for transmission to the LLC slice. We show that our proposal outperforms data prefetching mechanisms in a many-core processor due to (1) higher prediction accuracy and (2) not wasting valuable off-chip bandwidth, while requiring significantly less overhead. Using full-system simulation, we show that our proposal accelerates serving data misses by 22 percent and leads to 10 percent performance improvement over the state-of-the-art network-on-chip.

关键词： Memory system network-on-chip circuit switching data prefetching

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