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High performance Boson sampling simulation via data-flow engines

NEW JOURNAL OF PHYSICS 2024年第3期26卷 033033页

作者： Morse, Gregory Rybotycki, Tomasz Kaposi, Agoston Kolarovszki, Zoltan Stojcic, Uros Kozsik, Tamas Mencer, Oskar Oszmaniec, Michal Zimboras, Zoltan Rakyta, Peter Eotvos Lorand Univ Dept Programming Languages & Compilers Pazmany Peter Setany 1-a H-1117 Budapest Hungary Polish Acad Sci Nicolaus CopernicusAstron Ctr AstroCeNT Particle Astrophys Sci & Technol Ctr Int Res Agenda Warsaw Poland Univ Sci & Technol ACC Cyfronet Krakow Poland Syst Res Inst Polish Acad Sci Warsaw Poland Wigner Res Ctr Phys 29-33 Konkoly Thege Mikl Str H-1121 Budapest Hungary Maxeler Technol 16192 Coastal Hwy Lewes DE 19958 USA Polish Acad Sci Ctr Theoret Phys Warsaw Poland NASK Natl Res Inst Kolska 12 PL-01045 Warsaw Poland Algorithmiq Ltd Kanavakatu 3 C Helsinki 00160 Finland Eotvos Lorand Univ Dept Phys Complex Syst Pazmany Peter Setany 1-a H-1117 Budapest Hungary

Boson sampling (BS) is viewed to be an accessible quantum computing paradigm to demonstrate computational advantage compared to classical computers. In this context, the evolution of permanent calculation algorithms attracts a significant attention as the simulation of BS experiments involves the evaluation of vast number of permanents. For this reason, we generalize the Balasubramanian-Bax-Franklin-Glynn permanent formula, aiming to efficiently integrate it into the BS strategy of Clifford and Clifford (2020 Faster classical boson sampling). A reduction in simulation complexity originating from multiplicities in photon occupation was achieved through the incorporation of a n-ary Gray code ordering of the addends during the permanent evaluation. Implementing the devised algorithm on FPGA-based data-flow engines, we leverage the resulting tool to accelerate boson sampling simulations for up to 40 photons. Drawing samples from a 60-mode interferometer, the achieved rate averages around 80 s per sample, employing 4 FPGA chips. The developed design facilitates the simulation of both ideal and lossy boson sampling experiments.

关键词： boson sampling simulation FPGA permanent data-flow lossy boson sampling

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Towards data-flow Parallelization for Adaptive Mesh Refinement Applications 22

Towards Data-Flow Parallelization for Adaptive Mesh Refineme...

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IEEE International Conference on Cluster Computing

作者： Sala, Kevin Rico, Alejandro Beltran, Vicenc Barcelona Supercomp Ctr BSC Barcelona Spain Arm Res Austin TX USA

ISBN: (纸本)9781728166773

Adaptive Mesh Refinement (AMR) is a prevalent method used by distributed-memory simulation applications to adapt the accuracy of their solutions depending on the turbulent conditions in each of their domain regions. These applications are usually dynamic since their domain areas are refined or coarsened in various refinement stages during their execution. Thus, they periodically redistribute their workloads among processes to avoid load imbalance. Although the defacto standard for scientific computing in distributed environments is MPI, in recent years, pure MPI applications are being ported to hybrid ones, attempting to cope with modern multi-core systems. Recently, the Task-Aware MPI library was proposed to efficiently integrate MPI communications and tasking models, providing also the transparent management of communications issued by tasks. In this paper, we demonstrate the benefits of porting AMR applications to data-flow programming models leveraging that novel hybrid approach. We exploit most of the application parallelism by taskifying all stages, allowing their natural overlap. We employ these techniques on the miniAMR proxy application, which mimics the refinement, load balancing, communication, and computation patterns of general AMR applications. We evaluate how this approach reduces the time in its computation and communication phases while achieving better programmability than other conventional hybrid techniques.

关键词： Adaptive Mesh Refinement AMR MPI Tasks data-flow OpenMP OmpSs-2 TAMPI miniAMR

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SAT-based data-flow mapping onto array processor 28

SAT-based data-flow mapping onto array processor

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IFIP/IEEE 28th International Conference on Very Large Scale Integration (VLSI-SOC)

作者： Miyasaka, Yukio Fujita, Masahiro Univ Tokyo Tokyo Japan

ISBN: (纸本)9781728154091

Recently, it has been common to perform parallel processing in machine learning. Reconfigurable array processor is drawing attention in terms of easy custom adjustment and high performance. We propose a method to map a data-flow onto an array processor using a SAT solver. The proposed method is combined with an automatic transformation method, which changes the order of calculations, to generate a more efficient computation scheme. We have solved mapping problems of matrix-vector multiplication. In our experiment, a SAT solver was more scalable than an ILP solver. Our method handled a data-flow of more than a hundred nodes using MAC operation. The automatic transformation under the associative and commutative laws is less scalable but successfully reduced calculation time. We have also mapped sparse matrix multiplication with varying latency and throughput and generated faster schedules utilizing the sparsity.

关键词： SAT problem mapping data-flow reconfigurable processor

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Context-, flow-, and Field-Sensitive data-flow Analysis using Synchronized Pushdown Systems

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PROCEEDINGS OF THE ACM ON PROGRAMMING LANGUAGES-PACMPL 2019年第POPL期3卷 1-29页

作者： Spath, Johannes Ali, Karim Bodden, Eric Fraunhofer IEM Paderborn Germany Univ Alberta Edmonton AB Canada Univ Paderborn Heinz Nixdorf Inst Paderborn Germany

Precise static analyses are context-, field- and flow-sensitive. Context- and field-sensitivity are both expressible as context-free language (CFL) reachability problems. Solving both CH, problems along the same data-flow path is undecidable, which is why most flow-sensitive data-flow analyses over-approximate field-sensitivity through k-limited access-path, or through access graphs. Unfortunately, as our experience and this paper show, both representations do not scale very well when used to analyze programs with recursive data structures. Any single CFL-reachability problem is efficiently solvable, by means of a pushdown system. This work thus introduces the concept of synchronized pushdown systems (SPDS). SPDS encode both procedure calls/returns and field stores/loads as separate but "synchronized" CFL reachability problems. An SPDS solves both individual problems precisely, and approximation occurs only in corner cases that are apparently rare in practice: at statements where both problems are satisfied but not along the same data-flow path. SPDS are also efficient: formal complexity analysis shows that SPDS shift the complexity from vertical bar F vertical bar(3k) under k-limiting to vertical bar S vertical bar vertical bar F vertical bar(2), where F is the set of fields and S the set of statements involved in a data-flow. Our evaluation using DaCapo shows this shift to pay off in practice: SPDS are almost as efficient as k-limiting with k = 1 although their precision equals k = infinity. For a typestate analysis SPDS accelerate the analysis up to 83x for data-flows of objects that involve many field accesses but span rather few methods. We conclude that SPDS can provide high precision and further improve scalability, in particularly when used in analyses that expose rather local data flows.

关键词： static analysis data-flow aliasing access paths pushdown system

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Detection and Resolution of data-flow Differences in Business Process Models 1

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31st CAiSE Conference on Information Systems Engineering in Responsible Information Systems

作者： Jovanovikj, Ivan Yigitbas, Enes Gerth, Christian Sauer, Stefan Engels, Gregor Paderborn Univ SI Lab Software Innovat Lab Paderborn Germany Hsch Osnabruck Osnabruck Germany

ISBN: (数字)9783030212971

ISBN: (纸本)9783030212971;9783030212964

Business process models have an important role in enterprises and organizations as they are used for insight, specification or configuration of business processes. After its initial creation, a process model is very often refined, by different business modelers and software architects in distributed environments, in order to reflect changed requirements or changed business rules. At some point, the different resulting process model versions need to be merged in an integrated version. In order to enable comparison and merging, an approach which comprises difference representation as well as a discovery method for differences is needed. Regarding control-flow, such approaches already exist. As the specification of data-flow is also important, an approach for dealing with data-flow differences is also needed. In this paper, we propose a model for representation of data-flow differences as well as a method able to discover, visualize, and resolve data-flow differences.

关键词： Business process models data-flow Change management

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Evaluating data-flow coverage in spectrum-based fault localization 13

Evaluating data-flow coverage in spectrum-based fault locali...

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13th ACM/IEEE International Symposium on Empirical Software Engineering and Measurement (ESEM)

作者： Ribeiro, Henrique L. de Araujo, Roberto P. A. Chaim, Marcos L. de Souza, Higor A. Kon, Fabio Univ Sao Paulo Software Anal & Expt Grp SAEG Sch Arts Sci & Humanities Sao Paulo Brazil Univ Sao Paulo Dept Comp Sci Inst Math & Stat Sao Paulo Brazil

ISBN: (纸本)9781728129686

Background: Debugging is a key task during the software development cycle. Spectrum-based Fault Localization (SFL) is a promising technique to improve and automate debugging. SFL techniques use control-flow spectra to pinpoint the most suspicious program elements. However, data-flow spectra provide more detailed information about the program execution, which may be useful for fault localization. Aims: We evaluate the effectiveness and efficiency of ten SFL ranking metrics using data-flow spectra. Method: We compare the performance of data- and control-flow spectra for SFL using 163 faults from 5 real-world open source programs, which contain from 468 to 4130 test cases. The data- and control-flow spectra types used in our evaluation are definition-use associations (DUAs) and lines, respectively. Results: Using data-flow spectra, up to 50% more faults are ranked in the top-15 positions compared to control-flow spectra. Also, most SFL ranking metrics present better effectiveness using data-flow to inspect up to the top-40 positions. The execution cost of data-flow spectra is higher than control-flow, taking from 22 seconds to less than 9 minutes. dataflow has an average overhead of 353% for all programs, while the average overhead for control-flow is of 102%. Conclusions: The results suggest that SFL techniques can benefit from using data-flow spectra to classify faults in better positions, which may lead developers to inspect less code to find bugs. The execution cost to gather data-flow is higher compared to control-flow, but it is not prohibitive. Moreover, data-flow spectra also provide information about suspicious variables for fault localization, which may improve the developers' performance using SFL.

关键词： Fault localization Spectrum-based Debugging Structural testing data-flow Control-flow

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data Redundancy Problems in data-flow Computing and Solutions Implemented on the Recurrent Architecture

Data Redundancy Problems in Data-Flow Computing and Solution...

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IEEE Russia Section Young Researchers in Electrical and Electronic Engineering Conference (EIConRus)

作者： Shikunov, Yury Stepchenkov, Yury Khilko, Dmitry Shikunov, Dmitry Russian Acad Sci Adv Comp Syst Architectures Dept Fed Res Ctr Comp Sci & Control Inst Informat ProblemsIPI FRS CSC RASIPI RAS Moscow Russia

ISBN: (纸本)9781509048656

This paper covers one of the main disadvantages of data-flow computational model - high overhead costs associated with storing and processing large volumes of tag data. Overcoming this disadvantage using various ways of data compression comes with a number of problems described in this article. To solve given problems new recurrent data-flow computational model was created as well as architecture based on that model. This paper describes key features and mechanics of the new model and architecture allowing us to reduce data redundancy in memory storage. Efficiency of developed mechanics is shown in implementation of fast Fourier transform algorithm.

关键词： data-flow tagged data matching memory data compression

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Notifying Memories: a case-study on data-flow Applications with NoC Interfaces Implementation 16

Notifying Memories: a case-study on Data-Flow Applications w...

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53rd ACM/EDAC/IEEE Design Automation Conference (DAC)

作者： Martin, Kevin J. M. Rizk, Mostafa Sepulveda, Martha Johanna Diguet, Jean-Philippe Univ Bretagne Sud CNRS Lab STICC UMR 6285 F-56100 Lorient France Tech Univ Munich Inst Secur Informat Technol D-80290 Munich Germany

ISBN: (纸本)9781450342360

NoC-based architectures overcome the limitations of traditional buses by exploiting parallelism and offer large bandwidths. NoC adoption also increases communication latency, which is especially penalising for data-flow applications (DF). We introduce the notifying memories (NM) concept to reduce this overhead. Our original approach eliminates useless memory requests. This paper demonstrates NM in the context of video coding applications implemented with dynamic DF. We have conducted cycle accurate systemC simulation of the NoC on an MPEG4 decoder to evaluate NM efficiency. The results show significant reductions in terms of latency (78%), injection rate (60%), and power savings (49%) along with throughput improvement (16%).

关键词： NoC based architecture data-flow memory

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A scalable thread scheduling co-processor based on data-flow principles

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2015年 53卷 100-108页

作者： Giorgi, R. Scionti, A. Univ Siena Dept Informat Engn & Math I-53100 Siena Italy

Large synchronization and communication overhead will become a major concern in future extreme-scale machines (e.g., HPC systems, supercomputers). These systems will push upwards performance limits by adopting chips equipped with one order of magnitude more cores than today. Alternative execution models can be explored in order to exploit the high parallelism offered by future massive many-core chips. This paper proposes the integration of standard cores with dedicated co-processing units that enable the system to support a fine-grain data-flow execution model developed within the TERAFLUX project. An instruction set architecture extension for supporting fine-grain thread scheduling and execution is proposed. This instruction set extension is supported by the co-processor that provides hardware units for accelerating thread scheduling and distribution among the available cores. Two fundamental aspects are at the base of the proposed system: the programmers can adopt their preferred programming model, and the compilation tools can produce a large set of threads mainly communicating in a producer-consumer fashion, hence enabling data-flow execution. Experimental results demonstrate the feasibility of the proposed approach and its capability of scaling with the increasing number of cores. (C) 2015 Elsevier B.V. All rights reserved.

关键词： Co-processor architecture data-flow Many-core High-performance systems

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RFSoC Modulation Classification With Streaming CNN: data Set Generation & Quantized-Aware Training

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS

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IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS 2025年 6卷 38-49页

作者： Maclellan, Andrew Crockett, Louise H. Stewart, Robert W. Univ Strathclyde Dept Elect & Elect Engn StrathSDR Glasgow City Scotland

This paper introduces a novel FPGA-based Convolutional Neural Network (CNN) architecture for continuous radio data processing, specifically targeting modulation classification on the Zynq UltraScale+ Radio Frequency System on Chip (RFSoC) operating in real-time. Evaluated on AMD's RFSoC2x2 development board, the design integrates General Matrix Multiplication (GEMM) optimisations and fixed-point arithmetic. We also present a method for creating Deep Learning (DL) data sets for wireless communications, incorporating the RFSoC into the data generation loop. Furthermore, we explore quantised-aware training, producing three modulation classification models with different fixed-point weight precisions (16-bit, 8-bit, and 4-bit). We interface with the implemented hardware through the open-source PYNQ project, which combines Python with programmable logic interaction, enabling real-time modulation prediction via a PYNQ-enabled Jupyter app. The three models, operating at a 128 MHz sampling rate prior to the decimation stage, were evaluated for accuracy and resource consumption. The 16-bit model achieved the highest accuracy with minimal additional resource usage compared to the 8-bit and 4-bit models, making it the optimal choice for deploying a modulation classifier at the receiver.

关键词： Deep learning (DL) wireless communications AMD FPGA RFSoC PYNQ modulation classification convolutional neural network (CNN) inference data-flow general matrix multiplication (GEMM) transform data set generation artificial intelligence (AI) quantized-aware training

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