检索结果-内蒙古大学图书馆

CacheFlow: Cache Optimizations for data driven multithreading

PARALLEL PROCESSING LETTERS 2006年第2期16卷 229-244页

作者： Kyriacou, Costas Evripidou, Paraskevas Trancoso, Pedro Frederick Inst Technol Comp Engn Dept POB 24727 CY-1303 Nicosia Cyprus Univ Cyprus Dept Comp Sci CY-1678 Nicosia Cyprus

data-driven multithreading is a non-blocking multithreading model of execution that provides effective latency tolerance by allowing the computation processor do useful work, while a long latency event is in progress. With the data-driven multithreading model, a thread is scheduled for execution only if all of its inputs have been produced and placed in the processor's local memory. data-driven sequencing leads to irregular memory access patterns that could affect negatively cache performance. Nevertheless, it enables the implementation of short-term optimal cache management policies. This paper presents the implementation of CacheFlow, an optimized cache management policy which eliminates the side effects due to the loss of locality caused by the data-driven sequencing, and reduces further cache misses. CacheFlow employs thread-based prefetching to preload data blocks of threads deemed executable. Simulation results, for nine scientific applications, on a 32-node data-driven Multithreaded machine show an average speedup improvement from 19.8 to 22.6. Two techniques to further improve the performance of CacheFlow, conflict avoidance and thread reordering, are proposed and tested. Simulation experiments have shown a speedup improvement of 24% and 32%, respectively. The average speedup for all applications on a 32-node machine with both optimizations is 26.1.

关键词： Cache Management data-driven multithreading Prefetching

来源：评论

学校读者我要写书评

暂无评论

Toward data-driven architectural support in improving the performance of future HPC architectures

引用

PARALLEL COMPUTING 2019年第0期86卷 82-106页

作者： Matheou, George Soteriou, Vassos Evripidou, Paraskevas Univ Cyprus Dept Comp Sci Nicosia Cyprus Cyprus Univ Technol Dept Elect Engn Comp Engn & Informat Nicosia Cyprus

We propose architectures based on data-driven multithreading (DDM), a hybrid control-flow/data-flow model, to address the concurrency challenges faced by future High-Performance Computing (HPC) systems. We focus on the design and implementation of an optimized hardware Thread Scheduling Unit (TSU) and its integration into a multi-core system dubbed MiDAS. The TSU is the core of the DDM model and it orchestrates the execution of multiple threads on sequential processors based on data availability. MIDAS was prototyped on a Xilinx Virtex-6 FPGA and extensively evaluated using several micro benchmarks, showing that it achieves linearly-growing performance as the processing core count increases even when running benchmarks comprising very small problem sizes. Under the largest problem size tested and with all 8 available cores being utilized, MIDAS achieves an average speedup of 7.91x, exhibiting 98.8% utilization efficiency. Further, several results pertaining to the proposed hardware TSU are provided, including FPGA real estate requirements, where it is found that MiDAS's TSU demands relatively small overheads and reduced power consumption, while various TSU operations adhere to low latency responses. To back said claims, the proposed DDM-based TSU is compared with the Task Superscalar architecture that implements the StarSs programming framework in hardware. As such, comparison results show that the proposed TSU requires much less of both hardware investment and energy consumption to operate. Specifically, Task Superscalar is found to be 4.94 x larger than the DDM-supporting TSU in terms of slice register requirements and 11.34 x larger with respect to the slice look-up table count. Last, the hardware TSU is compared with a software TSU implementation offering identical functionalities, with both being run on an FPGA fabric under a synthetic application, where a detailed performance evaluation shows that MiDAS's hardware-implemented TSU significantly outperforms its

关键词： data-driven multithreading data-flow execution Multi-core architecture Hardware thread scheduler FPGA HPC

来源：评论

学校读者我要写书评

暂无评论

data-driven Concurrency for High Performance Computing

引用

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2017年第4期14卷 1–26页

作者： Matheou, George Evripidou, Paraskevas Univ Cyprus Nicosia Cyprus

In this work, we utilize dynamic dataflow/data-driven techniques to improve the performance of high performance computing (HPC) systems. The proposed techniques are implemented and evaluated through an efficient, portable, and robust programming framework that enables data-driven concurrency on HPC systems. The proposed framework is based on data-driven multithreading (DDM), a hybrid control-flow/dataflow model that schedules threads based on data availability on sequential processors. The proposed framework was evaluated using several benchmarks, with different characteristics, on two different systems: a 4-node AMD system with a total of 128 cores and a 64-node Intel HPC system with a total of 768 cores. The performance evaluation shows that the proposed framework scales well and tolerates scheduling overheads and memory latencies effectively. We also compare our framework to MPI, DDM-VM, and OmpSs@Cluster. The comparison results show that the proposed framework obtains comparable or better performance.

关键词： data-driven multithreading distributed execution runtime system high performance computing

来源：评论

学校读者我要写书评

暂无评论

data-driven Thread Execution on Heterogeneous Processors

引用

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2018年第2期46卷 198-224页

作者： Arandi, Samer Matheou, George Kyriacou, Costas Evripidou, Paraskevas An Najah Natl Univ Dept Comp Engn Nablus Palestine Univ Cyprus Dept Comp Sci Nicosia Cyprus Frederick Univ Dept Comp Sci & Engn Nicosia Cyprus

In this paper we report our experience in implementing and evaluating the data-driven multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program, allowing them to execute asynchronously in a dataflow manner. Thread dependencies are determined by the compiler/programmer while thread scheduling is done dynamically at runtime based on data availability. The target processor for this implementation is the Cell processor. We call this implementation the data-driven multithreading Virtual Machine for the Cell processor (DDM-). Thread scheduling is handled in software by the Power Processing Element core of the Cell while the Synergistic Processing Element cores execute the program threads. DDM- virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores, manages the Cell memory hierarchy efficiently and supports distributed execution across a cluster of Cell nodes. DDM- has been implemented on a single Cell processor with six computation cores, as well as, on a four Cell processor cluster with 24 computation cores. We present an in-depth performance analysis of DDM-, using a suite of standard computational benchmarks. The evaluation shows that DDM- scales well and tolerates scheduling overheads, memory and communication latencies effectively. Furthermore, DDM- compares favorably with other platforms targeting the Cell processor, such as, the CellSs and Sequoia.

关键词： Multi-core systems data-driven multithreading dataflow scheduling CacheFlow

来源：评论

学校读者我要写书评

暂无评论

Rapid Prototyping of the data-driven Chip-Multiprocessor (D-2-CMP) using FPGAs

引用

PARALLEL PROCESSING LETTERS 2008年第2期18卷 291-306页

作者： Tatas, Konstantinos Kyriacou, Costas Evripidou, Paraskevas Trancoso, Pedro Wong, Stephan Frederick Univ Comp Engn Dept POB 24727 CY-1303 Nicosia Cyprus Univ Cyprus Dept Comp Sci CY-1678 Nicosia Cyprus Delft Univ Technol Comp Engn Lab Delft Netherlands

This paper presents the FPGA implementation of the prototype for the data-driven Chip-Multiprocessor (D-2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking data-driven multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.

关键词： data-driven multithreading FPGA Multicore

来源：评论

学校读者我要写书评

暂无评论

TFluxSCC: Exploiting Performance on Future Many-core Systems through data-Flow 23

TFluxSCC: Exploiting Performance on Future Many-core Systems...

引用

23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

作者： Diavastos, Andreas Stylianou, Giannos Trancoso, Pedro Univ Cyprus Dept Comp Sci Nicosia Cyprus

ISBN: (纸本)9781479984909

The current trend in processor design is to increase the number of cores as to achieve a desired performance. While having a large number of cores on a chip seems to be feasible in terms of the hardware, the development of the software that is able to exploit that parallelism is one of the biggest challenges. In this paper we propose a data-Flow based system that can be used to exploit the parallelism in large-scale many-core processors in an effective and efficient way. Our proposed system - TFluxSCC - is an extension of the TFlux data-driven multithreading (DDM), which evolved to exploit the parallelism of the 48-core Intel Single-chip Cloud Computing (SCC) processor. With TFluxSCC we achieve scalable performance using a global address space without the need of cache-coherency support. Our scalability study shows that application's performance can scale, with speedup results reaching up to 48x for 48 cores. The findings of this work provide insight towards what a data-Flow implementation requires and what not from a many-core architecture in order to scale the performance.

关键词： dataflow many-cores programming model data-driven multithreading

来源：评论

学校读者我要写书评

暂无评论

A Run-time Manager for multithreading of Multi-core Systems

A Run-time Manager for Multithreading of Multi-core Systems

引用

Workshop on Computer Architecture, Embedded Systems, SoC, and VLSI/EDA / International Computer Symposium (ICS)

作者： Hsieh, Cheng Hung Jou, Jer Min Natl Cheng Kung Univ Dept Elect Engn Tainan Taiwan

ISBN: (纸本)9781614994848;9781614994831

The ubiquity of multi-core systems will necessitate time-efficient parallel execution of applications in a wide range of hardware and software environments. Compiled-time parallel execution can fail to be efficient and unable to account for dynamic changes in the multi-core run-time environment. In this paper, we propose a hardware-software co-design based run-time manager to dynamically, continuously and judiciously manage program's parallel execution in the dynamic execution conditions. It will schedule, map, synchronize, do load balance among workers of parallel applications in the multi-core environment efficiently. Experimental results show that the multiple programs could be executed simultaneously with 1.37x faster than their sequential version.

关键词： Multi-core System Parallel Execution of Sequential Program data-driven multithreading Run-time manager

来源：评论

学校读者我要写书评

暂无评论

Architectural Support for data-driven Execution

引用

ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2014年第4期11卷 52-52页

作者： Matheou, George Evripidou, Paraskevas Univ Cyprus Nicosia Cyprus

The exponential growth of sequential processors has come to an end, and thus, parallel processing is probably the only way to achieve performance growth. We propose the development of parallel architectures based on data-driven scheduling. data-driven scheduling enforces only a partial ordering as dictated by the true data dependencies, which is the minimum synchronization possible. This is very beneficial for parallel processing because it enables it to exploit the maximum possible parallelism. We provide architectural support for data-driven execution for the data-driven multithreading (DDM) model. In the past, DDM has been evaluated mostly in the form of virtual machines. The main contribution of this work is the development of a highly efficient hardware support for data-driven execution and its integration into a multicore system with eight cores on a Virtex-6 FPGA. The DDM semantics make barriers and cache coherence unnecessary, which reduces the synchronization latencies significantly and makes the cache simpler. The performance evaluation has shown that the support for data-driven execution is very efficient with negligible overheads. Our prototype can support very small problem sizes (matrix 16 x 16) and ultra-lightweight threads (block of 4x4) that achieve speedups close to linear. Such results cannot be achieved by software-based systems.

关键词： Prototyping Thread Scheduler Parallel Architectures Parallel Programming data-driven multithreading FPGA

来源：评论

学校读者我要写书评

暂无评论

Implementation of a Threaded dataflow Multiprocessor using FPGAs

Implementation of a Threaded Dataflow Multiprocessor using F...

引用

International Conference on Design & Technology of Integrated Systems in Nanoscale Era

作者： Konstantinos Tatas Costas Kyriacou Department of Computer Science and Engineering Frederick University Cyprus

ISBN: (纸本)9781612848990

This paper presents the FPGA implementation and evaluation of the prototype for a data-driven multithreading Chip-Multiprocessor. In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow rules on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e. a thread is fired only if its input data is available. This model of execution is called the non-blocking data-driven multithreading (DDM) model of execution. Due to its dataflow characteristics, this model exploits parallelism and tolerates latency. The DDM model has been evaluated using an execution driven simulator and showed and average speedup of 26 on a 32-node system. For evaluation purposes, implementation on Xilinx Virtex-5 FPGA using the Microblaze processors as execution cores has been performed. Experimental results show that the TSU can be implemented with a moderate hardware budget, and that delays incurred by the operation of the TSU can be tolerated. Furthermore, hardware complexity evaluation shows that the TSU size scales very well with the number of processors in the MPSoC.

关键词： Threaded dataflow data-driven multithreading FPGA Multicore

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：