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Reducing energy consumption using heterogeneous voltage frequency scaling of data-parallel applications for multicore systems

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2023年第1期175卷 121-133页

作者： Bratek, Pawel Szustak, Lukasz Wyrzykowski, Roman Olas, Tomasz Czestochowa Tech Univ Dept Comp Sci Dabrowskiego 69 PL-42201 Czestochowa Poland

This paper investigates the exploitation of heterogeneous DVFS (dynamic voltage frequency scaling) control for improving the energy efficiency of data-parallel applications on ccNUMA shared-memory systems. We propose to adjust the clock frequency individually for the appropriately selected groups of cores, taking into account the diversified costs of parallel computation. This paper aims to evaluate the proposed approach using two different data-parallel applications: solving the 3D diffusion problem, and MPdata fluid dynamics application. As a result, we observe the energy-savings gains of up to 20 percentage points over the traditional homogeneous frequency scaling approach on the server with two 18-core Intel Xeon Gold 6240. Additionally, we confirm the effectiveness of our strategy using two 64 - core AMD EPYC 7773X. This paper also introduces two pruning algorithms that help select the optimal heterogeneous DVFS setups taking into account the energy or performance profile of studied applications. Finally, the cost and efficiency of developed algorithms are verified and compared experimentally against the brute-force search.(c) 2023 Elsevier Inc. All rights reserved.

关键词： data-parallel applications Energy saving Heterogeneous voltage frequency scaling Multicore ccNUMA

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Acceleration of Bi-Objective Optimization of data-parallel applications for Performance and Energy on Heterogeneous Hybrid Platforms

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IEEE ACCESS 2023年 11卷 27226-27245页

作者： Manumachu, Ravi Reddy Khaleghzadeh, Hamidreza Lastovetsky, Alexey Univ Coll Dublin Sch Comp Sci Dublin 4 Ireland Univ Portsmouth Sch Comp Portsmouth PO1 2UP England

Accelerating the bi-objective optimization of applications for performance and energy is crucial to achieving energy efficiency objectives and meeting quality-of-service requirements in modern high-performance computing platforms and cloud computing infrastructures. In this work, we highlight the crucial challenges to accelerate model-based methods proposed for the bi-objective optimization of data parallel applications for performance and energy that employ workload distribution between the executing processors as the decision variable. The methods solve unconstrained bi-objective optimization problems and take input, the processors' performance and energy profiles in the form of discrete functions of workload size, and output Pareto-optimal solutions (workload distributions), minimizing the execution time and the total energy consumption of computations during the parallel execution of the application. One of the challenges is the fast computation of Pareto-optimal solutions. We then formulate the bi-objective optimization problem of data-parallel applications for performance and energy through workload distribution on a cluster of p identical hybrid nodes, each containing h heterogeneous processors. The state-of-the-art algorithm for solving the problem is sequential and takes exorbitant execution times to find Pareto-optimal solutions for even moderate numbers of processors. We propose two algorithms that address this shortcoming. The first algorithm is an exact sequential algorithm that is more efficient and amenable to parallelization and achieves a complexity reduction of O(m x h) over the state-of-the-art sequential algorithm where m is the cardinality of the input discrete execution time and dynamic energy functions. The second algorithm is a parallel algorithm executed by q identical parallel processes that reduces the complexity of our proposed sequential algorithm by O(q). It, therefore, achieves a complexity reduction of O(m x h x q) over the state-of-t

关键词： Heuristic algorithms Optimization Clustering algorithms High performance computing Graphics processing units Energy consumption Multicore processing Energy management High-performance heterogeneous computing energy-efficient computing bi-objective optimization performance optimization energy optimization data-parallel applications workload distribution

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A Novel data-Partitioning Algorithm for Performance Optimization of data-parallel applications on Heterogeneous HPC Platforms

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2018年第10期29卷 2176-2190页

作者： Khaleghzadeh, Hamidreza Manumachu, Ravindranath Reddy Lastovetsky, Alexey Univ Coll Dublin Sch Comp Sci Dublin 4 Ireland

Modem HPC platforms have become highly heterogeneous owing to tight integration of multicore CPUs and accelerators (such as Graphics Processing Units, Intel Xeon Phis, or Field-Programmable Gate Arrays) empowering them to maximize the dominant objectives of performance and energy efficiency. Due to this inherent characteristic, processing elements contend for shared on-chip resources such as Last Level Cache (LLC), interconnect, etc. and shared nodal resources such as DRAM, PCI-E links, etc. This has resulted in severe resource contention and Non-Uniform Memory Access (NUMA) that have posed serious challenges to model and algorithm developers. Moreover, the accelerators feature limited main memory compared to the multicore CPU host and are connected to it via limited bandwidth PCI-E links thereby requiring support for efficient out-of-card execution. To summarize, the complexities (resource contention, NUMA, accelerator-specific limitations, etc.) have introduced new challenges to optimization of data-parallel applications on these platforms for performance. Due to these complexities, the performance profiles of data-parallel applications executing on these platforms are not smooth and deviate significantly from the shapes that allowed state-of-the-art load-balancing algorithms to find optimal solutions. In this paper, we formulate the problem of optimization of data-parallel applications on modern heterogeneous HPC platforms for performance. We then propose a new model-based data partitioning algorithm, which minimizes the execution time of computations in the parallel execution of the application. This algorithm takes as input a set of p discrete speed functions corresponding to p available heterogeneous processors. It does not make any assumptions about the shapes of these functions. We prove the correctness of the algorithm and its complexity of O(m(3) x p(3)), where m is the cardinality of the input discrete speed functions. We experimentally demonstrate the op

关键词： Heterogeneous HPC platforms data-parallel applications data partitioning load balancing multicore CPU GPU Intel Xeon Phi performance optimization

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Bi-Objective Optimization of data-parallel applications on Heterogeneous HPC Platforms for Performance and Energy Through Workload Distribution

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 2021年第3期32卷 543-560页

作者： Khaleghzadeh, Hamidreza Fahad, Muhammad Shahid, Arsalan Manumachu, Ravi Reddy Lastovetsky, Alexey Univ Coll Dublin Sch Comp Sci Dublin 4 Ireland

Performance and energy are the two most important objectives for optimization on modern parallel platforms. In this article, we show that moving from single-objective optimization for performance or energy to their bi-objective optimization on heterogeneous processors results in a tremendous increase in the number of optimal solutions (workload distributions) even for the simple case of linear performance and energy profiles. We then study full performance and energy profiles of two real-life data-parallel applications and find that they exhibit shapes that are non-linear and complex enough to prevent good approximation of them as analytical functions for input to exact algorithms or optimization software for determining the Pareto front. We, therefore, propose a solution method solving the bi-objective optimization problem on heterogeneous processors. The method's novel component is an efficient and exact global optimization algorithm that takes as an input performance and energy profiles as arbitrary discrete functions of workload size, which accurately and realistically take into account resource contention and NUMA inherent in modern parallel platforms, and returns the Pareto-optimal solutions (generally speaking, load imbalanced). To construct the input discrete energy functions, the method employs a methodology that accurately models the energy consumption by a hybrid data-parallel application executing on a heterogeneous HPC platform containing different computing devices using system-level power measurements provided by power meters. We experimentally analyse the proposed solution method using three data-parallel applications, matrix multiplication, 2D fast Fourier transform (2D-FFT), and gene sequencing, on two connected heterogeneous servers consisting of multicore CPUs, GPUs, and Intel Xeon Phi. We show that it determines a superior Pareto front containing the best load balanced solutions and all the load imbalanced solutions that are ignored by load bala

关键词： Optimization Program processors Energy consumption Heuristic algorithms Multicore processing Software algorithms Sequential analysis Heterogeneous platforms data-parallel applications workload partitioning performance optimization energy optimization bi-objective optimization workload distribution multicore CPU GPU Intel Xeon Phi

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Heterogeneous Voltage Frequency Scaling of data-parallel applications for Energy Saving on Homogeneous Multicore Platforms 27th

Heterogeneous Voltage Frequency Scaling of Data-Parallel App...

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27th International European Conference on parallel and Distributed Computing (Euro-Par)

作者： Bratek, Pawel Szustak, Lukasz Wyrzykowski, Roman Olas, Tomasz Chmiel, Tomasz Czestochowa Tech Univ Dept Comp Sci Dabrowskiego 69 PL-42201 Czestochowa Poland

ISBN: (纸本)9783031061561;9783031061554

In this paper, for the first time, we explore and establish the combined benefits of heterogeneous DVFS (dynamic voltage frequency scaling) control in improving the energy-performance behavior of data-parallel applications on shared-memory multicore systems. We propose to customize the clock frequency individually for the appropriately selected groups of cores corresponding to the diversified time of actual computation. In consequence, the advantage of up to 20% points over the homogeneous frequency scaling is achieved on the ccNUMA server with two 18-core Intel Xeon Gold 6240 containing 72 logical cores in total. The cost and efficiency of the proposed pruning algorithm for selecting heterogeneous DVFS configurations against the brute-force search are verified and compared experimentally.

关键词： data-parallel applications Energy saving Heterogeneous voltage frequency scaling Multicore ccNUMA

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SDPA: An Optimizer for Program Analysis of data-parallel applications 20

SDPA: An Optimizer for Program Analysis of Data-Parallel App...

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20th IEEE International Conference on High Performance Computing and Communications (HPCC) / 16th IEEE International Conference on Smart City (SmartCity) / 4th IEEE International Conference on data Science and Systems (DSS)

作者： Wang, Fei Shi, Xuanhua Yu, Dongxiao Ke, Zhixiang Jin, Hai Wu, Song Huazhong Univ Sci & Technol Sch Comp Sci & Technol Serv Comp Technol & Syst Lab Big Data Technol & Syst Lab Wuhan 430074 Hubei Peoples R China

ISBN: (纸本)9781538666142

data-parallel applications have become prevalent due to the fast development of big data technologies. The performances of these applications are obviously one of the most crucial indexes cared about, while program analysis is a commonly used approach for program optimization. But because a great amount of complex operations, such as data partitioning, distribution, and parallelization, are included in the big data programming model, each data-parallel application is related to a great deal of complex framework code, even if the application is simple. If we analyze the application directly, it is very possible that effective results cannot be got even if consuming a large amount of time. Hence, we present an optimizer, called SDPA, to accelerate and simplify the program analysis of data-parallel applications. SDPA makes use of an important feature in data-parallel applications that the running processes have obvious stages. We implement SDPA to accelerate analysis specified in Spark. Extensive experiments are conducted to evaluate the performance and coverage of SDPA on some classical benchmark applications and real-world applications selected from MLlib. The evaluation results show that SDPA can 1) decrease the preprocessing time by 96.4% to 98.8%, 2) reduce the analysis time by approximately 99.8% compared with the approach of analyzing the entire data-parallel applications directly, and 3) cover majority of real-world applications.

关键词： data-parallel applications user defined function phase program analysis

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Simple super-matrix processor: Implementation and performance evaluation

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JOURNAL OF parallel AND DISTRIBUTED COMPUTING 2015年 83卷 96-118页

作者： Soliman, Mostafa I. Elsayed, Elsayed A. Taibah Univ Dept Informat & Comp Sci Community Coll Al Madinah Al Munawwarah Saudi Arabia Aswan Univ Dept Elect Engn Fac Engn Comp & Syst Sect Aswan 81542 Egypt

data-parallel applications are growing in importance and demanding increased performance from hardware. Since the fundamental data structures for a wide variety of data parallel applications are scalar, vector, and matrix, this paper proposes a simple matrix processor (SMP) for executing scalar, vector, and matrix instructions on a unified datapath. Matrix register file and matrix control unit are added to the decode stage of the well-known 5-stage pipeline (baseline scalar processor). To further improve the performance, a simple super-matrix processor (SSMP) is proposed to execute multi-scalar/vector/matrix instructions on parallel execution datapaths. 4 x 32-bit instructions are fetched, decoded, and checked for dependencies. Up to four independent scalar instructions can be issued in-order to the parallel execution units. However, vector/matrix instructions iterate the issuing of four vector/matrix operations without checking. 4 x 32-bit contiguous vector/matrix elements can be loaded/stored per clock cycle from/to L2 cache to/from matrix register file, however, scalar data can be accessed from L1 cache in a rate of one element per clock cycle. To prove our concept, the proposed SMP/SSMP are implemented on Xilinx Virtex-6 and evaluated on vector/matrix kernels. 8679/11734 slices are required for implementing SMP/SSMP, where the complexities are 2.79/3.77 times higher than the baseline scalar processor. However, the speedups of SMP/SSMP over the baseline scalar processor are 1.57-6.33/4.32-18.23. (C) 2015 Elsevier Inc. All rights reserved.

关键词： FPGA implementation data-parallel applications Vector/matrix processing Performance evaluation

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Collection-aware optimum sequencing of operations and closed-form solutions for the distribution of a divisible load on arbitrary processor trees

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1998年第5期9卷 429-441页

作者： Barlas, GD Natl Tech Univ Athens Dept Elect & Comp Engn GR-10682 Athens Greece

The problem of optimally distributing a divisible load to the nodes of an arbitrary processor tree is tackled in this paper. The rigorous mathematical foundation presented allows the derivation of the sequence of operations that is necessary to obtain the minimum processing time, along with closed-form expressions that yield the solution in time O(NP), where P is the number of tree nodes and N their maximum degree. The main contributions of this work are: (1) both load distribution and result collection overheads are considered, thus providing better resource utilization, and (2) arbitrary processor trees are examined in contrast with previous approaches that examined either complete homogeneous trees, or single level trees. Additionally approximate algorithms for solving the problem of specifying the optimum subset of active processors for a given load, are presented and evaluated.

关键词： optimum load distribution optimum distribution and collection sequencing data-parallel applications arbitrary processor trees collection-aware load distribution

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Fusion of loops for parallelism and locality

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IEEE TRANSACTIONS ON parallel AND DISTRIBUTED SYSTEMS 1997年第2期8卷 193-209页

作者： Manjikian, N Abdelrahman, TS Department of Electrical and Computer Engineering University of Toronto Toronto ONT Canada

Loop fusion improves data locality and reduces synchronization in data-parallel applications. However, loop fusion is not always legal. Even when legal, fusion may introduce loop-carried dependences which prevent parallelism. In addition, performance losses result from cache conflicts in fused loops. In this paper, we present new techniques to: 1) allow fusion of loop nests in the presence of fusion-preventing dependences, 2) maintain parallelism and allow the parallel execution of fused loops with minimal synchronization, and 3) eliminate cache conflicts in fused loops. We describe algorithms for implementing these techniques in compilers. The techniques are evaluated on a 56-processor KSR2 multiprocessor and on a 16-processor Convex SPP-1000 multiprocessor. The results demonstrate performance improvements for both kernels and complete applications. The results also indicate that careful evaluation of the profitability of fusion is necessary as more processors are used.

关键词： locality enhancement loop fusion cache conflicts loop transformation data-parallel applications scalable shared-memory multiprocessors

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PROSE: Multi-round fair coflow scheduling without prior knowledge

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COMPUTER COMMUNICATIONS 2023年第1期209卷 163-177页

作者： Zhang, Fan Tang, Yazhe Li, Xun Hu, Chengchen Xi An Jiao Tong Univ Sch Comp Sci & Technol Xian 710049 Peoples R China Sci & Technol Commun Networks Lab Shijiazhuang Hebei Peoples R China NIO Shanghai 201804 Peoples R China

Coflow scheduling plays a crucial role in enhancing network-level performance in datacenter applications. Existing works on coflow scheduling predominantly concentrate on clairvoyant schedulers, which assume prior knowledge of coflow sizes before transmission. However, this assumption is often unrealistic in practical scenarios like pipelined computation. Consequently, research on non-clairvoyant schedulers has garnered increasing attention. Most studies on non-clairvoyant schedulers focus on either improving efficiency or promoting fairness, with limited emphasis on striking a balance between the two objectives. Additionally, for non-cooperative environments like multi-tenant datacenter networks, it is essential to ensure strategy-proofness in coflow scheduling. Without adequate measures, tenants may manipulate their reported requirements to gain an unfair advantage in resource allocation. Ideally, in non-cooperative environments, a coflow scheduler should achieve efficiency, fairness, and strategy-proofness, all without prior knowledge of coflow sizes. However, few existing efforts have managed to simultaneously achieve these objectives. To fill this gap, we develop PROSE, a non-clairvoyant scheduler for non-cooperative environments. PROSE divides the scheduling time into multiple rounds and employs a two-stage scheduling mechanism based on these rounds. In the first stage, PROSE estimates the sizes of the coflows with unknown sizes by transmitting the probe flows, using a policy that combines coflow competition with batch processing. Once the information about coflow sizes is obtained, PROSE prioritizes coflows among tenants for bandwidth allocation in the second stage, aiming to accelerate coflow completion within each round. Furthermore, PROSE ensures optimal isolation guarantee by fairly limiting the total data transfer for each tenant and dynamically adjusts the scheduling order of coflows in a round-robin manner across multiple rounds. PROSE prevents tenants

关键词： Coflow Non-clairvoyant scheduler datacenter networks data-parallel applications Strategy-proofness

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