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High-performance dataflow computing in hybrid memory systems with UPC plus plus DepSpawn

JOURNAL OF SUPERcomputing 2021年第7期77卷 7676-7689页

作者： Fraguela, Basilio B. Andrade, Diego Univ A Coruna CITIC Res Ctr Informat & Commun Technol La Coruna 15071 Spain

dataflow computing is a very attractive paradigm for high-performance computing, given its ability to trigger computations as soon as their inputs are available. UPC++ DepSpawn is a novel task-based library that supports this model in hybrid shared/distributed memory systems on top of a Partitioned Global Address Space environment. While the initial version of the library provided good results, it suffered from a key restriction that heavily limited its performance and scalability. Namely, each process had to consider all the tasks in the application rather than only those of interest to it, an overhead that naturally grows with both the number of processes and tasks in the system. In this paper, this restriction is lifted, enabling our library to provide higher levels of performance. This way, in experiments using 768 cores the performance improved up to 40.1%, the average improvement being 16.1%.

关键词： dataflow computing Hybrid parallelism PGAS Runtimes Programability High-performance computing

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The Case for Polymorphic Registers in dataflow computing

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2018年第6期46卷 1185-1219页

作者： Ciobanu, Catalin Bogdan Gaydadjiev, Georgi Pilato, Christian Sciuto, Donatella Univ Amsterdam Syst & Network Engn Grp Amsterdam Netherlands Delft Univ Technol Distributed Syst Grp Delft Netherlands Maxeler Technol Ltd London England Univ Lugano Fac Informat Lugano Switzerland Politecn Milan Dip Elettron Informaz & Bioingn Milan Italy

Heterogeneous systems are becoming increasingly popular, delivering high performance through hardware specialization. However, sequential data accesses may have a negative impact on performance. Data parallel solutions such as Polymorphic Register Files (PRFs) can potentially accelerate applications by facilitating high-speed, parallel access to performance-critical data. This article shows how PRFs can be integrated into dataflow computational platforms. Our semi-automatic, compiler-based methodology generates customized PRFs and modifies the computational kernels to efficiently exploit them. We use a separable 2D convolution case study to evaluate the impact of memory latency and bandwidth on performance compared to a state-of-the-art NVIDIA Tesla C2050GPU. We improve the throughput upto 56.17X and show that the PRF-augmented system outperforms the GPU for for 9 x 9 or larger mask sizes, even in bandwidth-constrained systems.

关键词： dataflow computing Parallel memory accesses Polymorphic register file Bandwidth Vector lanes Convolution High performance computing High-level synthesis

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Programmable dataflow computing on PCA

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2000年第12期E83A卷 2409-2416页

作者： Imlig, N Shiozawa, T Konishi, R Oguri, K Nagami, K Ito, H Inamori, M Nakada, H Nippon Telegraph & Tel Corp Network Innovat Labs Yokosuka Kanagawa 2390847 Japan Nagasaki Univ Dept Comp & Informat Sci Nagasaki 8528521 Japan

This paper introduces a flexible. stream oriented dataflow processing model based on the "Communicating Logic (CL)" framework. As the target architecture, wt adopt the dual layered "Plastic Cell Architecture (PCA)." Datapath processing functionality is encapsulated in asynchronous hardware objects with variable graining and implemented rising look-up tables. Communication (i.e. connectivity and control) between the distributed processing objects is achieved bq means of inter-object message passing. The key point of the CL approach is that it offers the merits uf scalable performance. low power hardware implementation with the user friendly compilation and linking capabilities unique to software.

关键词： programmable logic devices dataflow computing parallel processing plastic cell architecture

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On communication efficient dataflow computing in software defined networking enabled cloud

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2021年第7期33卷 1-1页

作者： Li, Yuepeng Zeng, Deze Zheng, Long China Univ Geosci Hubei Key Lab Intelligent Geoinformat Proc Sch Comp Sci Wuhan Hubei Peoples R China Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China

dataflow computing has become a promising computing paradigm as an alternative to traditional control-centric computing paradigm to facilitate big data processing. Big data process often happens in cloud computing environment as the datacenter provisions a large amount of resource. dataflow computing, as a data-centric computing paradigm, requires the dataflows to be shuffled among different codelets (ie, data processing units) deployed in the datacenter servers. It is significant to well schedule the dataflow transferring for communication efficiency. It is highly regarded that the datacenter network shall be managed by software defined networking (SDN) technology for flexibility consideration. In SDN managed datacenter, a dataflow requires a forwarding rule in the forwarding table of each switch on its routing path. However, the SDN switches are limited in the forwarding table size. This introduces an unignorable issue in the codelet deployment problem. Therefore, we are motivated to take such forwarding table size constraints into the problem of dataflow codelet deployment in the datacenters managed by SDN. In particular, we aim at minimizing the communication cost efficiency while guarantee the dataflow computing performance at the same time. The communication cost minimization problem is formulated into an integer linear programming form, which is relaxed to design a heuristic algorithm. The experiment results show that our relaxation algorithm can significantly improve the communication cost efficiency via ingenious codelet placement.

关键词： codelet deployment dataflow computing software defined networking virtual network embedding

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ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing

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CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE 2019年第18期31卷

作者： Penha, Jeronimo C. Silva, Lucas B. Silva, Jansen M. Coelho, Kristtopher K. Baranda, Hector P. Nacif, Jose Augusto M. Ferreira, Ricardo S. Univ Fed Vicosa Comp Sci Dept Vicosa MG Brazil Univ Fed Vicosa Sci & Technol Inst UFV Florestal Campus Vicosa MG Brazil Ctr Fed Educ Tecnol Minas Gerais Comp Sci & Mech Engn Dept Leopoldina Campus Belo Horizonte MG Brazil

dataflow-based FPGA accelerators have become a promising alternative to deliver energy-efficient high-performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high-level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high-level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low-cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high-level programming languages, and it has been validated on two FPGA platforms: the Intel high-performance CPU-FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi-core and GPU accelerators.

关键词： dataflow computing FPGA accelerators heterogeneous architectures high-performance computing overlay

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A software cache autotuning strategy for dataflow computing with UPC plus plus DepSpawn

COMPUTATIONAL AND MATHEMATICAL METHODS

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COMPUTATIONAL AND MATHEMATICAL METHODS 2021年第6期3卷

作者： Fraguela, Basilio B. Andrade, Diego Univ A Coruna CITIC Ctr Singular Invest Galicia Comp Architecture Grp La Coruna Spain

dataflow computing allows to start computations as soon as all their dependencies are satisfied. This is particularly useful in applications with irregular or complex patterns of dependencies which would otherwise involve either coarse grain synchronizations which would degrade performance, or high programming costs. A recent proposal for the easy development of performant dataflow algorithms in hybrid shared/distributed memory systems is UPC++ DepSpawn. Among the many techniques it applies to provide good performance is a software cache that minimizes the communications among the processes involved. In this article we provide the details of the implementation and operation of this cache and we present an autotuning strategy that simplifies its usage by freeing the user from having to estimate an adequate size for this cache. Rather, the runtime is now able to define reasonably sized caches that provide near optimal behavior.

关键词： autotuning dataflow computing distributed memory locality PGAS runtimes

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MAXIMUM PERFORMANCE computing WITH dataflow ENGINES

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computing IN SCIENCE & ENGINEERING 2012年第4期14卷 98-103页

作者： Pell, Oliver Averbukh, Vitali Univ London Imperial Coll Sci Technol & Med Dept Phys London SW7 2AZ England

Multidisciplinary dataflow computing is a powerful approach to scientific computing that has led to orders-of-magnitude performance improvements for a wide range of applications.

关键词： Computational Modeling Computer Architecture Computational Algorithms Scientific computing Data Processing Computer Architectures Computational Modeling Computer Architecture Computational Algorithms Scientific computing Data Processing Scientific computing dataflow computing Exascale Processing Computational Science

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Productivity, Portability, Performance, and Reproducibility: Data-Centric Python

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 2025年第5期36卷 804-820页

作者： Ziogas, Alexandros Nikolaos Schneider, Timo Ben-Nun, Tal Calotoiu, Alexandru De Matteis, Tiziano de Fine Licht, Johannes Lavarini, Luca Hoefler, Torsten Swiss Fed Inst Technol Dept Informat Technol & Elect Engn CH-8092 Zurich Switzerland Swiss Fed Inst Technol Dept Comp Sci CH-8092 Zurich Switzerland Lawrence Livermore Natl Lab Ctr Appl Sci Comp Livermore CA 94550 USA Vrije Univ Amsterdam Dept Comp Sci NL-1081 HV Amsterdam Netherlands NextSilicon CH-8005 Zurich Switzerland 1plusX CH-8005 Zurich Switzerland

Python has become the de facto language for scientific computing. Programming in Python is highly productive, mainly due to its rich science-oriented software ecosystem built around the NumPy module. As a result, the demand for Python support in High-Performance computing (HPC) has skyrocketed. However, the Python language itself does not necessarily offer high performance. This work presents a workflow that retains Python's high productivity while achieving portable performance across different architectures. The workflow's key features are HPC-oriented language extensions and a set of automatic optimizations powered by a data-centric intermediate representation. We show performance results and scaling across CPU, GPU, FPGA, and the Piz Daint supercomputer (up to 23,328 cores), with 2.47x and 3.75x speedups over previous-best solutions, first-ever Xilinx and Intel FPGA results of annotated Python, and up to 93.16% scaling efficiency on 512 nodes. Our benchmarks were reproduced in the Student Cluster Competition (SCC) during the Supercomputing Conference (SC) 2022. We present and discuss the student teams' results.

关键词： Productivity Codes Semantics Computer architecture Supercomputers Software Field programmable gate arrays Optimization Python Computer languages high-performance computing dataflow computing parallel programming distributed computing distributed computing

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LOW-POWER HETEROGENEOUS computing VIA ADAPTIVE EXECUTION OF dataflow ACTORS

LOW-POWER HETEROGENEOUS COMPUTING VIA ADAPTIVE EXECUTION OF ...

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IEEE International Workshop on Signal Processing Systems (SiPS)

作者： Boutellier, Jani Bhattacharyya, Shuvra S. Tampere Univ Technol Lab Pervas Comp Tampere Finland Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

ISBN: (纸本)9781538604465

dataflow models of computation have been shown to provide an excellent basis for describing signal processing applications and mapping them to heterogeneous computing platforms that consist of multicore CPUs and graphics processing units (GPUs). Recently several efficient dataflow-based programming frameworks have been introduced for such needs. Most of contemporary signal processing applications can be described using static dataflow models of computation (e.g. synchronous dataflow) that have desirable features such as compile-time analyzability. Unfortunately, static dataflow models of computation turn out to be restrictive when applications need to adapt their behavior to varying conditions at run-time, such as power saving through adaptive processing. This paper analyzes three dataflow approaches for implementing adaptive application behavior in terms of expressiveness and efficiency. The focus of the paper is on heterogeneous computing platforms and particularly on adapting application processing for achieving power saving. Experiments are conducted with deep neural network and dynamic predistortion applications on two platforms: a mobile multicore SoC and a GPU-equipped workstation.

关键词： dataflow computing signal processing parallel processing graphics processing units deep neural networks

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PRUNE: Dynamic and Decidable dataflow for Signal Processing on Heterogeneous Platforms

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2018年第3期66卷 654-665页

作者： Boutellier, Jani Wu, Jiahao Huttunen, Heikki Bhattacharyya, Shuvra S. Tampere Univ Technol Lab Pervas Comp Tampere 33720 Finland Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Tampere Univ Technol Lab Signal Proc Tampere 33720 Finland

The majority of contemporary mobile devices and personal computers are based on heterogeneous computing platforms that consist of a number of CPU cores and one or more graphics processing units (GPUs). Despite the high volume of these devices, there are few existing programming frameworks that target full and simultaneous utilization of all CPU and GPU devices of the platform. This article presents a dataflow-flavored model of computation (MoC) that has been developed for deploying signal processing applications to heterogeneous platforms. The presented MoC is dynamic and allows describing applications with data dependent run-time behavior. On top of the MoC, formal design rules are presented that enable application descriptions to be simultaneously dynamic and decidable. Decidability guarantees compile-time application analyzability for deadlock freedom and bounded memory. The presented MoC and the design rules are realized in a novel Open Source programming environment "PRUNE" and demonstrated with representative application examples from the domains of image processing, computer vision and wireless communications. Experimental results show that the proposed approach outperforms the state-of-the-art in analyzability, flexibility, and performance.

关键词： dataflow computing design automation signal processing parallel processing

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