检索结果-内蒙古大学图书馆

A General-Purpose Many-Accelerator Architecture Based on dataflow graph Clustering of Applications

Journal of Computer Science & Technology 2014年第2期29卷 239-246页

作者：陈鹏张磊韩银和陈云霁 State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences University of Chinese Academy of Sciences

The combination of growing transistor counts and limited power budget within a silicon die leads to the utilization wall problem （a.k.a. ＂Dark Silicon＂）, that is only a small fraction of chip can run at full speed during a period of time. Designing accelerators for specific applications or algorithms is considered to be one of the most promising approaches to improving energy-efficiency. However, most current design methods for accelerators are dedicated for certain applications or algorithms, which greatly constrains their applicability. In this paper, we propose a novel general-purpose many-accelerator architecture. Our contributions are two-fold. Firstly, we propose to cluster dataflow graphs （DFGs） of hotspot basic blocks （BBs） in applications. The DFG clusters are then used for accelerators design. This is because a DFC is the largest program unit which is not specific to a certain application. We analyze 17 benchmarks in SPEC CPU 2006, acquire over 300 DFGs hotspots by using LLVM compiler tool, and divide them into 15 clusters based on graph similarity. Secondly, we introduce a function instruction set architecture （FISC） and illustrate how DFG accelerators can be integrated with a processor core and how they can be used by applications. Our results show that the proposed DFG clustering and FISC design can speed up SPEC benchmarks 6.2X on average.

关键词： dataflow graph many-accelerator clustering function instruction set architecture

来源：评论

学校读者我要写书评

暂无评论

Automatic design of application specific instruction set extensions through dataflow graph exploration

引用

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2003年第6期31卷 429-449页

作者： Clark, N Zhong, HT Tang, WK Mahlke, S Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

General-purpose processors are often incapable of achieving the challenging cost, performance, and power demands of high-performance applications. To meet these demands, most systems employ a number of hardware accelerators to off-load the computationally demanding portions of the application. As an alternative to this strategy, we examine customizing the computation capabilities of a processor for a particular application. The processor is extended with hardware in the form of a set of custom function units and instruction set extensions. To effectively identify opportunities for creating custom hardware, a dataflow graph design space exploration engine heuristically identifies candidate computation subgraphs without artificially constraining their size or shape. The engine combines estimates of performance gain, cost, and inherent limitations of the processor to grow candidate graphs in profitable directions while pruning unprofitable paths. This paper describes the dataflow graph exploration engine and evaluates its effectiveness across a set of embedded applications.

关键词： application-specific processor dataflow graph embedded system hardware customization instruction set

来源：评论

学校读者我要写书评

暂无评论

Performance Model for Parallel Matrix Multiplication with Dryad: dataflow graph Runtime

Performance Model for Parallel Matrix Multiplication with Dr...

引用

2nd International Conference on Cloud and Green Computing / 2nd International Conference on Social Computing and its Applications (CGC/SCA)

作者： Li, Hui Fox, Geoffrey Qiu, Judy Indiana Univ Bloomington Sch Informat & Comp Pervas Technol Inst Bloomington IN USA

ISBN: (纸本)9780769548647;9781467330275

In order to meet the big data challenge of today's society, several parallel execution models on distributed memory architectures have been proposed: MapReduce, Iterative MapReduce, graph processing, and dataflow graph processing. Dryad is a distributed data-parallel execution engine that model program as dataflow graphs. In this paper, we evaluated the runtime and communication overhead of Dryad in realistic settings. We proposed a performance model for Dryad implementation of parallel matrix multiplication (PMM) and extend the model to MPI implementations. We conducted experimental analyses in order to verify the correctness of our analytic model on a Windows cluster with up to 400 cores, Azure with up to 100 instances, and Linux cluster with up to 100 nodes. The final results show that our analytic model produces accurate predictions within 5% of the measured results. We proved some cases that using average communication overhead to model performance of parallel matrix multiplication jobs on common HPC clusters is the practical approach.

关键词： Dryad dataflow graph Performance Modeling MPI Matrix Multiplication

来源：评论

学校读者我要写书评

暂无评论

MULTIDIMENSIONAL dataflow graph MODELING AND MAPPING FOR EFFICIENT GPU IMPLEMENTATION

MULTIDIMENSIONAL DATAFLOW GRAPH MODELING AND MAPPING FOR EFF...

引用

IEEE Workshop on Signal Processing Systems (SiPS)

作者： Wang, Lai-Huei Shen, Chung-Ching Seetharaman, Gunasekaran Palaniappan, Kannappan Bhattacharyya, Shuvra S. Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA Air Force Res Lab Rome NY USA Univ Missouri Columbia Columbia MD USA

ISBN: (纸本)9780769548562;9781467329866

Multidimensional synchronous dataflow (MDSDF) provides an effective model of computation for a variety of multidimensional DSP systems that have static dataflow structures. In this paper, we develop new methods for optimized implementation of MDSDF graphs on embedded platforms that employ multiple levels of parallelism to enhance performance at different levels of granularity. Our approach allows designers to systematically represent and transform multi-level parallelism specifications from a common, MDSDF-based application level model. We demonstrate our methods with a case study of image histogram implementation on a graphics processing unit (GPU). Experimental results from this study show that our approach can be used to derive fast GPU implementations, and enhance trade-off analysis during design space exploration.

关键词： dataflow graph multidimensional synchronous dataflow graphics processing unit integral histogram

来源：评论

学校读者我要写书评

暂无评论

Translating of MATLAB/SIMULINLK Model to Synchronous dataflow graph for Parallelism Analysis and Programming Embedded Multicore Systems 9

Translating of MATLAB/SIMULINLK Model to Synchronous Dataflo...

引用

9th International Design & Test Symposium (IDT)

作者： Guesmi, Kaouther Hasnaoui, Salem Univ Tunis Al Manar Natl Sch Engn Tunis ENIT SYSCOM Res Lab Tunis Tunisia

ISBN: (纸本)9781479982004

Software implementation of compute-intensive applications in digital signal processing requires large computing power and has real-time performance requirements. Employing multicore architecture is usually the only means for solving the grand challenge of computational problems. Developing multicore-based systems requires a high degree of concurrency for optimizing performances of systems. For this purpose, this paper addresses the redesigning of MATLAB\Simulink models for efficient concurrent implementation using multiple processors. Our approach consists of translating a Simulink model into discrete synchronous dataflow graph in order to treat them as concurrent system by exploiting task-level parallelism without alter the input-output behavior of the system.

关键词： multicore embedded systems dataflow graph MATLAB/Simulink

来源：评论

学校读者我要写书评

暂无评论

Automatic design of application specific instruction set extensions through dataflow graph exploration

Automatic design of application specific instruction set ext...

引用

Workshop on Application Specific Processors (WASP-02)

作者： Clark, N Zhong, HT Tang, WK Mahlke, S Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

关键词： application-specific processor dataflow graph embedded system hardware customization instruction set

来源：评论

学校读者我要写书评

暂无评论

Programmable Real-Time Scheduling of Disaggregated Network Functions: A Theoretical Model

引用

IEEE TRANSACTIONS ON NETWORK AND SERVICE MANAGEMENT 2025年第1期22卷 485-498页

作者： Levai, Tamas Vass, Balazs Retvari, Gabor Budapest Univ Technol & Econ HUN REN BME Informat Syst Res Grp H-1111 Budapest Hungary Budapest Univ Technol & Econ Dept Math & Comp Sci Hungarian Line HUN REN BME Informat Syst Res Grp H-1111 Budapest Hungary Babes Bolyai Univ Cluj Napoca 400347 Romania

Novel telecommunication systems build on a cloudified architecture running softwarized network services as disaggregated virtual network functions (VNFs) on commercial off-the-shelf (COTS) hardware to improve costs and flexibility. Given the stringent processing deadlines of modern applications, these systems are critically dependent on a closed-loop control algorithm to orchestrate the execution of the disaggregated components. At the moment, however, the formal model for implementing such real-time control loops is mostly missing. In this paper, we introduce a new real-time VNF execution environment that runs entirely on COTS hardware. First, we define a comprehensive formal model that enables us to reason about packet processing delays across disaggregated VNF processing chains analytically. Then we integrate the model into a gradient-optimization control algorithm to provide optimal scheduling for real-time infocommunication services in a programmable way. We present experimental evidence that our model gives a proper delay estimation on a real software switch. We evaluate our control algorithm on multiple representative use cases using a software switch simulator. Our results show the algorithm drives the system to a real-time capable state in just a few control periods even in case of complex services.

关键词： Real-time systems Software Switches Delays Hardware Optimal scheduling Pipelines Software algorithms Costs Telecommunications dataflow graph software switch SDN NFV

来源：评论

学校读者我要写书评

暂无评论

dataflow graphs as complete causal graphs 2

Dataflow graphs as complete causal graphs

引用

IEEE/ACM 2nd International Conference on AI Engineering - Software Engineering for AI (CAIN)

作者： Paleyes, Andrei Guo, Siyuan Scholkopf, Bernhard Lawrence, Neil D. Univ Cambridge Dept Comp Sci & Technol Cambridge England Max Planck Inst Intelligent Syst Stuttgart Germany

ISBN: (纸本)9798350301137

Component-based development is one of the core principles behind modern software engineering practices. Understanding of causal relationships between components of a software system can yield significant benefits to developers. Yet modern software design approaches make it difficult to track and discover such relationships at system scale, which leads to growing intellectual debt. In this paper we consider an alternative approach to software design, flow-based programming (FBP), and draw the attention of the community to the connection between dataflow graphs produced by FBP and structural causal models. With expository examples we show how this connection can be leveraged to improve day-to-day tasks in software projects, including fault localisation, business analysis and experimentation.

关键词： flow-based programming causal inference dataflow graph root cause analysis experimentation

来源：评论

学校读者我要写书评

暂无评论

Response modeling runtime schedulers for timing analysis of self-timed dataflow graphs

引用

JOURNAL OF SYSTEMS ARCHITECTURE 2016年 65卷 15-29页

作者： Lele, Alok Moreira, Orlando Cuijpers, Pieter J. L. van Berkel, Kees TU Eindhoven Dept Math & Comp Sci Eindhoven Netherlands Intel BV Eindhoven Netherlands

Constituent tasks of modern day Embedded Streaming Applications (ESAs), such as engine control systems, multimedia and software defined radios often exhibit execution behaviors that do not conform to conventional task models. ESAs consist of iterative, pipelined sequences of tasks that are conditioned by intra- and inter-iteration dependencies, and often have strict throughput and latency requirements. We model ESAs as dataflow graphs, where actors represent computational units, and directed edges represent communication channels between actors. Due to practical constraints like cost-effectiveness, power consumption and chip-area, multiple ESAs are run on a shared (multi-processor) platform. Thus rigorous timing analysis is required to verify whether individual ESAs meet their respective timing requirements. We look at response modeling, a compositional timing analysis approach wherein the local worst-case influence of runtime scheduling is represented within the constructs provided in dataflow. These local representations (called response models) can be composed together to construct a global understanding of an ESA's worst-case execution which is then used to verify whether its real-time requirements are met. This paper proposes a generic response modeling technique for runtime scheduling of ESAs. We focus on preemptive Fixed Priority Scheduling (FPS) but also demonstrate that we can apply our technique to a wide range of runtime schedulers. In our experiments, we present academic and industrial case-studies that highlight the effectiveness of our approach in the timing analysis of ESAs with unconventional execution behavior. (C) 2016 Elsevier B.V. All rights reserved.

关键词： dataflow graph Runtime scheduling Timing analysis

来源：评论

学校读者我要写书评

暂无评论

Visualizing dataflow graphs of Deep Learning Models in TensorFlow

引用

IEEE TRANSACTIONS ON VISUALIZATION AND COMPUTER graphICS 2018年第1期24卷 1-12页

作者： Wongsuphasawat, Kanit Smilkov, Daniel Wexler, James Wilson, Jimbo Mane, Dandelion Fritz, Doug Krishnan, Dilip Viegas, Fernanda B. Wattenberg, Martin Univ Washington Paul G Allen Sch Comp & Engn Seattle WA 98195 USA Google Res Mountain View CA USA

We present a design study of the TensorFlow graph Visualizer, part of the TensorFlow machine intelligence platform. This tool helps users understand complex machine learning architectures by visualizing their underlying dataflow graphs. The tool works by applying a series of graph transformations that enable standard layout techniques to produce a legible interactive diagram. To declutter the graph. we decouple non-critical nodes from the layout. To provide an overview, we build a clustered graph using the hierarchical structure annotated in the source code. To support exploration of nested structure on demand. we perform edge bundling to enable stable and responsive cluster expansion. Finally, we detect and highlight repeated structures to emphasize a model's modular composition. To demonstrate the utility of the visualizer, we describe example usage scenarios and report user feedback. Overall, users find the visualizer useful for understanding, debugging, and sharing the structures of their models.

关键词： Neural Network graph Visualization dataflow graph Clustered graph

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：