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Efficient Computation of the Max-Plus Semantics of Synchronous dataflow graphs

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2023年第10期42卷 3412-3425页

作者： Elahi, Hossein Geilen, Marc Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5612 AZ Eindhoven Netherlands TNO ESI NL-5656 AE Eindhoven Netherlands

Streaming systems are naturally modeled with synchronous dataflow graphs (SDFGs). The max-plus semantics of an SDFG is a compact matrix representation of its timing behavior. The max-plus semantics enables us to analyze and control timing properties of the systems, such as the obtainable minimum guaranteed throughput and maximum latency. Deriving the max-plus semantics, and consequently, performance analysis may be computationally expensive since the state-of-the-art method simulates one iteration of an SDFG. This holds, in particular, for systems whose components operate at different levels of granularity, as this results in many executions of some components in one iteration. This article aims at efficiently calculating the max-plus semantics of SDFGs. This article proposes an optimization framework exploring decompositions of a given SDFG and finding a composition sequence whose computational effort for compositionally obtaining the max-plus semantics is minimal. Not only does our proposed technique accelerate the performance analysis of multiscale streaming systems, but it also allows us to compute the max-plus semantics of some systems for which the state-of-the-art method does not succeed because of memory limitations.

关键词： Semantics Computational modeling Transform coding Streaming media Decoding Optimization Throughput dataflow graphs max-plus semantics multiscale systems performance analysis streaming systems

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Automatic Task Parallelization of dataflow graphs in ML/DL Models 38

Automatic Task Parallelization of Dataflow Graphs in ML/DL M...

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International Parallel and Distributed Processing Symposium (IPDPS)

作者： Das, Srinjoy Rauchwerger, Lawrence Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9798350387117;9798350387124

Several methods exist today to accelerate Machine Learning(ML) or Deep-Learning(DL) model performance for training and inference. However, modern techniques that rely on various graph and operator parallelism methodologies rely on search space optimizations which are costly in terms of power and hardware usage. Especially in the case of inference, when the batch size is 1 and execution is on CPUs, or for power-constrained edge devices, current techniques can become costly, complicated or inapplicable. To ameliorate this, we present a Critical-Path-based Linear Clustering approach to exploit inherent parallel paths in ML dataflow graphs. Our task parallelization approach further optimizes the structure of graphs via cloning and prunes them via constant propagation and dead-code elimination. Contrary to other work, we generate readable and executable parallel Pytorch+Python code from input ML models in ONNX format via a new tool that we have built called Ramiel. This allows us to benefit from other downstream acceleration techniques like intra-op parallelism and potentially pipeline parallelism. Our preliminary results on several ML graphs demonstrate up to 1.9x speedup over serial execution and outperform some of the current mechanisms in both compile and runtimes. Lastly, our methods are lightweight and fast enough so that they can be used effectively for power and resource-constrained devices, while still enabling downstream optimizations.

关键词： Machine/Deep Learning ML models dataflow graphs Parallelization Clustering Pytorch ONNX

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Allocation and Scheduling of dataflow graphs on Hybrid dataflow/von Neumann Architectures 23

Allocation and Scheduling of Dataflow Graphs on Hybrid Dataf...

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21st ACM/IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE)

作者： Bhagyanath, Anoop Kercher, Nadine Schneider, Klaus RPTU Kaiserslautern Landau Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9798400703188

Hybrid dataflow/von Neumann processors expose their processing units and datapaths to the compiler to exploit the instruction-level parallelism of sequential programs. Generating code from dataflow graphs for such processors that use FIFO-buffered datapaths requires (1) an allocation that maps the nodes of the dataflow graph to the processing units (PUs) of the processor, and (2) a schedule for firing the nodes on the PUs that does not violate the FIFO behavior of the buffers. In previous work, we have encoded the constraints required to ensure the FIFO behavior for the code generation as a SAT problem. In this paper, we consider PU allocation and node scheduling in isolation, inspired by the traditional compilers, which also treat register allocation and instruction scheduling as separate problems. If a schedule is given, we reduce the PU allocation problem to a graph coloring problem so that heuristics can solve it efficiently. We also perform interference analysis, similar to register interference analysis to reveal special properties of the PU allocation graph. If a PU allocation is given, the scheduling problem is almost reduced to a 2SAT problem so that it can also be solved efficiently.

关键词： dataflow graphs dataflow computing code generation exposed datapath architectures

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Consistency Constraints for Mapping dataflow graphs to Hybrid dataflow/von Neumann Architectures

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2023年第5期22卷 81-81页

作者： Schneider, Klaus Bhagyanath, Anoop RPTU Kaiserslautern Landau Dept Comp Sci Gottlieb Daimler Str D-67663 Kaiserslautern Germany

dataflow process networks (DPNs) provide a convenient model of computation that is often used to model system behavior in model-based designs. With fixed sets of nodes, they are also used as dataflow graphs as an intermediate program representation by compilers to uncover instruction-level parallelism of sequential programs. Many recent processor architectures, which are still von Neumann architectures, also use dataflow computing to increase their exploitation of instruction-level parallelism by exposing their datapaths so that the compiler can take care of the allocation of processing units (PUs), the execution schedules of instructions on the PUs, and the communication of intermediate values between PUs. If the communication paths are buffered, these architectures can be abstracted into a DPN architecture whose PUs and interconnection network are DPN nodes. In this article, we introduce a DPN abstraction of hybrid dataflow/von Neumann architectures and consider the mapping of the nodes of a given dataflow graph to the PUs of such a DPN architecture such that there are no conflicts due to the mapping of different nodes to the same PU. We express the allocation and scheduling constraints in terms of propositional logic for the original dataflow graph and for a modified version of the dataflow graph that simplifies the constraints by introducing levels using copy nodes, such that all nodes receive inputs only from nodes of the previous level. We also formulate equisatisfiable SMT constraints using integer variables to reason directly about the parallel runtime. On this basis, we further present alternative SAT constraints that explicitly encode concurrency, and discuss variants of the constraints for a better understanding of the same.

关键词： dataflow graphs code generation exposed datapath architectures linear graph layouts queue layouts

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Code Generation Criteria for Buffered Exposed Datapath Architectures from dataflow graphs 2022

Code Generation Criteria for Buffered Exposed Datapath Archi...

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23rd International Conference on Languages, Compilers, and Tools for Embedded System (LCTES)

作者： Schneider, Klaus Bhagyanath, Anoop Roob, Julius Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781450392662

Many novel processor architectures expose their processing units (PUs) and internal datapaths to the compiler. To avoid an unnecessary synchronization of PUs, the datapaths are often buffered which results in buffered exposed datapath (BED) architectures. This paper suggests a code generation technique for BED architectures from dataflow graphs that are used as intermediate program representations. Inspired by results on queue layouts in graph drawing, we determine in this paper constraints for the node and edge orderings of the dataflow graphs to ensure the first-in-first-out behavior of the buffers. Formalizing these constraints in propositional logic enables SAT solvers to compute optimal PU allocations. Moreover, future code generation techniques may develop heuristics based on the code generation criteria of this paper.

关键词： dataflow graphs code generation exposed datapath architectures linear graph layouts queue layouts

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Incremental Analysis of Cyclo-Static Synchronous dataflow graphs

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2015年第4期14卷 68-68页

作者： De Groote, Robert Holzenspies, Philip K. E. Kuper, Jan Smit, Gerard J. M. Univ Twente Fac EEMCS NL-7500 AE Enschede Netherlands Facebook Menlo Pk CA 94025 USA

In this article, we present a mathematical characterisation of admissible schedules of cyclo-static dataflow (CSDF) graphs. We demonstrate how algebra ic manipulation of this characterization is related to unfolding CSDF actors and how this manipulation allows CSDF graphs to be transformed into MRSDF graphs that are equivalent, in the sense that they admit the same set of schedules. The presented transformation allows the rich set of existing analysis techniques for MRSDF graphs to be applied to CSDF graphs and generalizes the well-known transformations from CSDF and MRSDF into HSDF. Moreover, it gives rise to an incremental approach to the analysis of CSDF graphs, where approximate analyses are combined with exact transformations. We show the applicability of this incremental approach by demonstrating its effectiveness on the problem of optimizing buffer sizes under a throughput constraint.

关键词： Analysis dataflow graphs cyclo-static synchronous

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PARTIAL EXPANSION OF dataflow graphs FOR RESOURCE-AWARE SCHEDULING OF MULTICORE SIGNAL PROCESSING SYSTEMS 48

PARTIAL EXPANSION OF DATAFLOW GRAPHS FOR RESOURCE-AWARE SCHE...

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48h Asilomar Conference on Signals, Systems and Computers

作者： Zaki, George Plishker, William Bhattacharyya, Shuvra S. Fruth, Frank Univ Maryland ECE Dept College Pk MD 20742 USA Univ Maryland UMIACS College Pk MD 20742 USA Texas Instruments Inc Multicore & Commun Infrastruct Business Unit Germantown MD USA

ISBN: (纸本)9781479982974

The complex design spaces associated with state-of-the-art, multicore signal processing systems pose significant challenges in realizing designs with high productivity and quality. The Partial Expansion Graph (PEG) implementation model was developed to help address these challenges by enabling more efficient exploration of the scheduling design space for multicore digital signal processors. The PEG allows designers and design tools to systematically adjust and adapt the amount of parallelism exposed from applications depending on the targeted platform. In this paper, we develop new algorithms for scheduling and mapping systems implemented using PEGs. Collectively, these algorithms operate in three steps. First, the amount of data parallelism in the application graph is tuned systematically over many iterations to profit from the available cores in the target platform. Then a mapping algorithm that uses graph analysis is developed to distribute data and task parallel instances over different cores while trying to balance the load of all processing units to make use of pipeline parallelism. Finally, we use a novel technique for performance evaluation by implementing the scheduler and a customizable solution on the programmable platform. We demonstrate the utility of our PEG-based scheduling and mapping algorithms through experiments on real application models and various synthetic graphs.

关键词： dataflow graphs Digital Signal Processing Multiprocessor Scheduling Dynamic Scheduling

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A Binary Translation Framework for Automated Hardware Generation

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IEEE MICRO 2021年第4期41卷 15-22页

作者： Paulino, Nuno Bispo, Joao Ferreira, Joao C. Cardoso, Joao M. P. Inst Engn Sistemas & Computadores Tecnol & Cienci P-4200465 Porto Portugal Univ Porto Fac Engn P-4200465 Porto Portugal

As applications move to the edge, efficiency in computing power and power/energy consumption is required. Heterogeneous computing promises to meet these requirements through application-specific hardware accelerators. Runtime adaptivity might be of paramount importance to realize the potential of hardware specialization, but further study is required on workload retargeting and offloading to reconfigurable hardware. This article presents our framework for the exploration of both offloading and hardware generation techniques. The framework is currently able to process instruction sequences from MicroBlaze, ARMv8, and riscv32imaf binaries, and to represent them as Control and dataflow graphs for transformation to implementations of hardware modules. We illustrate the framework's capabilities for identifying binary sequences for hardware translation with a set of 13 benchmarks.

关键词： Field Programmable Gate Arrays Graph Theory Hardware Accelerators Low Power Electronics Power Consumption Reconfigurable Architectures Reduced Instruction Set Computing Energy Consumption Power Consumption dataflow graphs AR Mv 8 Micro Blaze Hardware Translation Binary Sequences Hardware Modules Riscv 32 Imaf Binaries Instruction Sequences Hardware Generation Techniques Reconfigurable Hardware Workload Retargeting Hardware Specialization Runtime Adaptivity Application Specific Hardware Accelerators Heterogeneous Computing Automated Hardware Generation Binary Translation Framework Field Programmable Gate Arrays Hardware Runtime Market Research Transistors Energy Consumption Table Lookup Energy Management

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Buffer Minimization in Earliest-Deadline First Scheduling of dataflow graphs

Buffer Minimization in Earliest-Deadline First Scheduling of...

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14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems

作者： Bouakaz, Adnan Talpin, Jean-Pierre Univ Rennes 1 IRISA F-35014 Rennes France

ISBN: (纸本)9781450320856

Symbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific scheduling policy. Furthermore, the resulted schedule must ensure that communication buffers are underflow- and overflow-free. This paper describes a (partitioned) earliest-deadline first symbolic schedulability analysis of dataflow graphs that minimizes the buffering requirements. Our scheduling analysis consists of three major steps. (1) The construction of an abstract affine schedule of the graph that excludes overflow and underflow exceptions and minimizes the buffering requirements assuming some precedences between jobs. (2) Symbolic deadlines adjustment that guarantees precedences without the need for lock-based synchronizations. (3) The concretization of the affine schedule using a symbolic, fast-converging, processor-demand analysis for both uniprocessor and multiprocessor systems. Experimental results show that our technique improves the buffering requirements in many cases.

关键词： Theory Algorithms Design dataflow graphs Symbolic schedulability analysis Buffer minimization Affine relation Earliest-deadline first scheduling

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Buffer minimization in earliest-deadline first scheduling of dataflow graphs 13

Buffer minimization in earliest-deadline first scheduling of...

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Proceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems

作者： Adnan Bouakaz Jean-Pierre Talpin University of Rennes 1/IRISA Rennes France INRIA / IRISA Rennes France

ISBN: (纸本)9781450320856

Symbolic schedulability analysis of dataflow graphs is the process of synthesizing the timing parameters (i.e. periods, phases, and deadlines) of actors so that the task system is schedulable and achieves a high throughput when using a specific scheduling policy. Furthermore, the resulted schedule must ensure that communication buffers are underflow- and overflow-free. This paper describes a (partitioned) earliest-deadline first symbolic schedulability analysis of dataflow graphs that minimizes the buffering *** scheduling analysis consists of three major steps. (1) The construction of an abstract affine schedule of the graph that excludes overflow and underflow exceptions and minimizes the buffering requirements assuming some precedences between jobs. (2) Symbolic deadlines adjustment that guarantees precedences without the need for lock-based synchronizations. (3) The concretization of the affine schedule using a symbolic, fast-converging, processor-demand analysis for both uniprocessor and multiprocessor systems. Experimental results show that our technique improves the buffering requirements in many cases.

关键词： dataflow graphs affine relation earliest-deadline first scheduling buffer minimization symbolic schedulability analysis

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