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International Conference on Embedded Software (EMSOFT)

作者： Bebelis, Vagelis Fradet, Pascal Girault, Alain Lavigueur, Bruno INRIA Rhone Alpes Villeurbanne France STMicroelect Grenoble Grenoble France

ISBN: (纸本)9781479914432

dataflow programming models are well-suited to program many-core streaming applications. However, many streaming applications have a dynamic behavior. To capture this behavior, parametric dataflow models have been introduced over the years. Still, such models do not allow the topology of the dataflow graph to change at runtime, a feature that is also required to program modern streaming applications. To overcome these restrictions, we propose a new model of computation, the Boolean Parametric Data Flow (BPDF) model which combines integer parameters (to express dynamic rates) and boolean parameters (to express the activation and deactivation of communication channels). High dynamism is provided by integer parameters which can change at each basic iteration and boolean parameters which can even change within the iteration. The major challenge with such dynamic models is to guarantee liveness and boundedness. We present static analyses which ensure statically the liveness and the boundedness of BDPF graphs. We also introduce a scheduling methodology to implement our model on highly parallel platforms and demonstrate our approach using a video decoder case study.

关键词： dataflow model Dynamism Parameters Liveness Boundedness Scheduling

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Codelet Pipe: Realization of dataflow Software Pipelining for Extended Codelet model 23

Codelet Pipe: Realization of Dataflow Software Pipelining fo...

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52nd International Conference on Parallel Processing (ICPP)

作者： Raskar, Siddhisanket Applencourt, Thomas Kumaran, Kalyan Gao, Guang Argonne Natl Lab Lemont IL 60439 USA Univ Delaware Newark DE USA

ISBN: (纸本)9798400708428

dataflow Software Pipelining for Codelet model is a coarse-grained code-mapping scheme designed to exploit pipelined parallelism across Codelets executing on different cores. The extended operational semantics of the Codelet model exploit pipelined parallelism across loops (coarse-grained) using single owner FIFO buffers across Codelet's dependencies. The extended Codelet model with dataflow Software Pipelining extensions has shown promising performance benefits by leveraging FIFO buffers to communicate between producer and consumer codelets. These performance gains can be further amplified using an efficient implementation of FIFO buffers using hardware-software co-design principles for an architecture that supports explicit access to scratchpad memory closer to compute cores. In this work, we introduce Codelet Pipe which serves as an efficient hardware-software co-designed communication channel between producer-consumer codelets to take advantage of dataflow software pipelining for codelet model. The current implementation of Codelet Pipe exploits Shared Local Memory architectural feature of Intel Iris Pro GPU using OpenCL. Codelet Pipe enables users to construct well-structured Codelet Graphs as well as helps with the challenge of ease of Programmability by relieving user from the responsibility of handling communication between producerconsumer codelet pairs. We demonstrate performance gains using a set of micro-benchmarks for a GPU architecture of strategic importance for exascale supercomputers.

关键词： dataflow model dataflow Software Pipelining Hardware-Software Co-design Extended Codelet model Codelet Pipe Programmability Many-core Architecture exa-scale

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Position Paper: Extending Codelet model for dataflow Software Pipelining using Software-Hardware Co-Design 43

Position Paper: Extending Codelet Model for Dataflow Softwar...

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43rd IEEE-Computer-Society Annual International Computers, Software and Applications Conference (COMPSAC)

作者： Raskar, Siddhisanket Applencourt, Thomas Kumaran, Kalyan Gao, Guang Argonne Natl Lab Lemont IL 60439 USA Univ Delaware Newark DE 19716 USA

ISBN: (纸本)9781728126074

Trends in processor and system architecture, driven by power and complexity, point super-computing landscape toward very high and heterogeneous core count designs. As the number of cores inevitably increase traditional ways of performing large scale computations will also need to evolve from legacy models like OpenMP & MPI. However, such models are very much wedded to a control-flow vision of parallel programs, making it difficult to express asynchrony in programs. To address these challenges, codelet model was developed which is fine-grained, event-driven asynchronous program execution model. In-spite of its initial design goals, the Codelet model is rife with opportunities for further improvements to provide high-performance for both data and control regular applications. The major inspiration behind this work is to leverage the decades of research done to exploit instruction level parallelism (ILP) for the machine instructions inside codelet while build upon the dataflow software pipelining principals at codelet graph level to further enhance performance. In this paper, we propose hardware assisted extensions to the original codelet program execution model in order to implement efficient dataflow software pipelining and extend capabilities of the codelet model. This hardware-software co-design focuses on efficient implementation of data FIFO buffers leveraging proposed optimizations like - FIFO ring buffers and multiple-head FIFO buffers and single owner FIFO buffers to further exploit advantages of dataflow software pipelining. The wide range of scientific, machine learning and specially streaming applications should be able to take advantage of techniques proposed in this paper. Identifying these kernels and bench-marking them are the next anticipated steps for us.

关键词： dataflow model Software Pipelining dataflow Software Pipelining Codelet model Program Execution model Many-core Architecture FIFO Buffer Exa-scale

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A Pipelining Loop Optimization Method for dataflow Architecture

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Journal of Computer Science & Technology 2018年第1期33卷 116-130页

作者： Xu Tan Xiao-Chun Ye Xiao-Wei Shen Yuan-Chao Xu Da Wang Lunkai Zhang Wen-Ming Li Dong-Rui Fan Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing 1000J9 China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125 China College of Information Engineering Capital Normal University Beijing 100048 China Department of Computer Science The University of Chicago Chicago IL 60637 U.S.A.

With the coming of exascale supercomputing era, power efficiency has become the most important obstacle to build an exascale system. dataflow architecture has native advantage in achieving high power efficiency for scientific applications. However, the state-of-the-art dataflow architectures fail to exploit high parallelism for loop processing. To address this issue, we propose a pipelining loop optimization method （PLO）, which makes iterations in loops flow in the processing element （PE） array of dataflow accelerator. This method consists of two techniques, architecture-assisted hardware iteration and instruction-assisted software iteration. In hardware iteration execution model, an on-chip loop controller is designed to generate loop indexes, reducing the complexity of computing kernel and laying a good f（mndation for pipelining execution. In software iteration execution model, additional loop instructions are presented to solve the iteration dependency problem. Via these two techniques, the average number of instructions ready to execute per cycle is increased to keep floating-point unit busy. Simulation results show that our proposed method outperforms static and dynamic loop execution model in floating-point efficiency by 2.45x and 1.1x on average, respectively, while the hardware cost of these two techniques is acceptable.

关键词： dataflow model control-flow model loop optimization exascale computing scientific application

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Accelerating Data Transfer in dataflow Architectures Through a Look-Ahead Acknowledgment Mechanism

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Journal of Computer Science & Technology 2022年第4期37卷 942-959页

作者： Yu-Jing Feng De-Jian Li Xu Tan Xiao-Chun Ye Dong-Rui Fan Wen-Ming Li Da Wang Hao Zhang Zhi-Min Tang State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China Beijing Smartchip Microelectronics Technology Company Limited Beijing 100000China School of Computer and Control Engineering University of Chinese Academy of SciencesBeijing 100190China

The dataflow architecture,which is characterized by a lack of a redundant unified control logic,has been shown to have an advantage over the control-flow architecture as it improves the computational performance and power efficiency,especially of applications used in high-performance computing(HPC).Importantly,the high computational efficiency of systems using the dataflow architecture is achieved by allowing program kernels to be activated in a simultaneous ***,a proper acknowledgment mechanism is required to distinguish the data that logically belongs to different *** solutions include the tagged-token matching mechanism in which the data is sent before acknowledgments are received but retried after rejection,or a handshake mechanism in which the data is only sent after acknowledgments are ***,these mechanisms are characterized by both inefficient data transfer and increased area *** performance of the dataflow architecture depends on the efficiency of data *** order to optimize the efficiency of data transfer in existing dataflow architectures with a minimal increase in area and power cost,we propose a Look-Ahead Acknowledgment(LAA)*** accelerates the execution flow by speculatively acknowledging ahead without *** simulation analysis based on a handshake mechanism shows that our LAA increases the average utilization of computational units by 23.9%,with a reduction in the average execution time by 17.4%and an increase in the average power efficiency of dataflow processors by 22.4%.Crucially,our novel approach results in a relatively small increase in the area and power consumption of the on-chip logic of less than 0.9%.In conclusion,the evaluation results suggest that Look-Ahead Acknowledgment is an effective improvement for data transfer in existing dataflow architectures.

关键词： dataflow model control-flow model high-performance computing application data transfer power efficiency

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Distilling structure in Taverna scientific workflows: a refactoring approach

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BMC BIOINFORMATICS 2014年第1-Sup期15卷 1-14页

作者： Cohen-Boulakia, Sarah Chen, Jiuqiang Missier, Paolo Goble, Carole Williams, Alan R. Froidevaux, Christine Univ Paris 11 CNRS UMR 8623 Lab Rech Informat Orsay France INRIA Saclay AMIB Grp Palaiseau France Lanzhou Univ Sch Informat Sci & Engn Lanzhou 730000 Gansu Peoples R China Univ Newcastle Callaghan NSW 2308 Australia Univ Manchester Manchester M13 9PL Lancs England

Background: Scientific workflows management systems are increasingly used to specify and manage bioinformatics experiments. Their programming model appeals to bioinformaticians, who can use them to easily specify complex data processing pipelines. Such a model is underpinned by a graph structure, where nodes represent bioinformatics tasks and links represent the dataflow. The complexity of such graph structures is increasing over time, with possible impacts on scientific workflows reuse. In this work, we propose effective methods for workflow design, with a focus on the Taverna model. We argue that one of the contributing factors for the difficulties in reuse is the presence of "anti-patterns", a term broadly used in program design, to indicate the use of idiomatic forms that lead to over-complicated design. The main contribution of this work is a method for automatically detecting such anti-patterns, and replacing them with different patterns which result in a reduction in the workflow's overall structural complexity. Rewriting workflows in this way will be beneficial both in terms of user experience (easier design and maintenance), and in terms of operational efficiency (easier to manage, and sometimes to exploit the latent parallelism amongst the tasks). Results: We have conducted a thorough study of the workflows structures available in Taverna, with the aim of finding out workflow fragments whose structure could be made simpler without altering the workflow semantics. We provide four contributions. Firstly, we identify a set of anti-patterns that contribute to the structural workflow complexity. Secondly, we design a series of refactoring transformations to replace each anti-pattern by a new semantically-equivalent pattern with less redundancy and simplified structure. Thirdly, we introduce a distilling algorithm that takes in a workflow and produces a distilled semantically-equivalent workflow. Lastly, we provide an implementation of our refactoring approach t

关键词： Output Port Input Port Recursive Call Trace Link dataflow model

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Parallel Scheduling of Multiple SDF Graphs Onto Heterogeneous Processors

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IEEE ACCESS 2021年 9卷 20493-20507页

作者： Jeong, Dowhan Kim, Jangryul Oldja, Mari-Liis Ha, Soonhoi TmaxA&C Seongnam 13613 South Korea Seoul Natl Univ Dept Comp Engn Seoul 08826 South Korea

Parallel scheduling of multiple real-time applications onto heterogeneous processors is needed in the emerging embedded systems such as self-driving cars, smart cameras, and smartphones. Assuming that an embedded application is specified as a synchronous dataflow (SDF) graph or its extension, we propose a novel parallel scheduling methodology based on an evolutionary algorithm where the mapping of tasks onto processors is evolved to optimize a given objective function in an iterative fashion. In each iteration, we use an existing worst-case response time (WCRT) analysis tool to check if all applications satisfy their real-time requirements by translating each SDF graph into a directed acyclic graph (DAG) that is assumed in the WCRT analysis tool. Since the WCRT analysis must be performed in each iteration of evolution, we propose a clustering technique to reduce drastically the analysis time that depends on the number of nodes and their dependency. We formally prove that the proposed clustering technique does not change the estimated WCRT of each application. The effectiveness of the proposed scheduling methodology with the clustering technique is verified with extensive experiments using real-life benchmarks, randomly generated graphs, and the comparison with the existing technique.

关键词： Task analysis Processor scheduling Real-time systems Tools Program processors Optimal scheduling Scheduling Mapping and scheduling design space exploration dataflow model model transformation performance analysis worst-case response time

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The Renoir dataflow Platform: Efficient Data Processing without Complexity

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FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE 2024年 160卷 472-488页

作者： De Martini, Luca Margara, Alessandro Cugola, Gianpaolo Donadoni, Marco Morassutto, Edoardo Politecn Milan Piazza Leonardo da Vinci 32 I-20133 Milan Italy

Today, data analysis drives the decision-making process in virtually every human activity. This demands for software platforms that offer simple programming abstractions to express data analysis tasks and that can execute them in an efficient and scalable way. State-of-the-art solutions range from low-level programming primitives, which give control to the developer about communication and resource usage, but require significant effort to develop and optimize new algorithms, to high-level platforms that hide most of the complexities of parallel and distributed processing, but often at the cost of reduced efficiency. To reconcile these requirements, we developed Renoir, a novel distributed data processing platform written in Rust. Renoir provides a high-level dataflow programming model as mainstream data processing systems. It supports static and streaming data, it enables data transformations, grouping, aggregation, iterative computations, and time-based analytics, and it provides all these features incurring in a low overhead. In this paper, we present the programming model and the implementation details of Renoir. We evaluate it under heterogeneous workloads. We compare it with state-of-the-art solutions for data analysis and high-performance computing, as well as alternative research products, which offer different programming abstractions and implementation strategies. Renoir programs are compact and easy to write: developers need not care about low-level concerns such as resource usage, data serialization, concurrency control, and communication. At the same time, Renoir consistently presents comparable or better performance than competing solutions, by a large margin in several scenarios. We conclude that Renoir offers a good tradeoff between simplicity and performance, allowing developers to easily express complex data analysis tasks and achieve high performance and scalability.

关键词： Data analytics Distributed processing Batch processing Stream processing dataflow model

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Carrying on the legacy of imperative languages in the future parallel computing era

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PARALLEL COMPUTING 2014年第3-4期40卷 1-33页

作者： Selim, Mohammad Reza Rahman, Mohammed Ziaur Shahjalal Univ Sci & Technol Dept Comp Sci & Engn Sylhet 3114 Bangladesh Zifern Ltd Kuala Lumpur 59200 Malaysia

There has been a renewed interest in *** models in recent years of technology scaling. Potentiality of exploiting huge parallelism, with the expense of low power, simpler circuit, less silicon area, is the main characteristic of a dataflow model. Growing trends in housing large number of functional units in a single chip, making use of local clocks, reducing energy consumptions, avoiding global wires are the main reasons behind the resurgence of dataflow models. To program a dataflow machine, new architectures suggest imperative languages rather than functional type dataflow languages or parallel languages because this is the right way to make the new architectures popular among the general community. Although for several decades scientists have been working on how imperative languages can be used in dataflow models efficiently, there is no systematic review on those works. Existing reviews on dataflow paradigm mainly focus on the architectures. Although few papers review programming languages of dataflow architectures, their discussions are limited to only dataflow languages and visual programming languages which are fundamentally different from imperative languages. In this paper, we conduct a systematic review on those works that attempt to provide a way to use imperative languages in any type of dataflow architectures. Our survey of compilers and related architectures cover the aspects like translation mechanisms of program construct, their optimization techniques, memory ordering methods, program allocation and scheduling and special architectural features. We also present some of our observations and future research directions obtained by exploring the literature. (c) 2014 Elsevier B.V. All rights reserved.

关键词： dataflow computing dataflow model Parallel computing High performance computing Imperative language Compiler

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The LONI Pipeline Processing Environment

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NEUROIMAGE 2003年第3期19卷 1033-1048页

作者： Rex, DE Ma, JQ Toga, AW Univ Calif Los Angeles David Geffen Sch Med Dept Neurol Lab Neuroimaging Los Angeles CA 90095 USA

The analysis of raw data in neuroimaging has become a computationally entrenched process with many intricate steps run on increasingly larger datasets. Many software packages exist that provide either complete analyses or specific steps in an analysis. These packages often possess diverse input and output requirements, utilize different file formats, run in particular environments, and have limited abilities with certain types of data. The combination of these packages to achieve more sensitive and accurate results has become a common tactic in brain mapping studies but requires much work to ensure valid interoperation between programs. The handling, organization, and storage of intermediate data can prove difficult as well. The LONI Pipeline Processing Environment is a simple, efficient, and distributed computing solution to these problems enabling software inclusion from different laboratories in different environments. It is used here to derive a T1-weighted MRI atlas of the human brain from 452 normal young adult subjects with fully automated processing. The LONI Pipeline Processing Environment's parallel processing efficiency using an integrated client/server dataflow model was 80.9% when running the atlas generation pipeline from a PC client (Acer TravelMate 340T) on 48 dedicated server processors (Silicon Graphics Inc. Origin 3000). The environment was 97.5% efficient when the same analysis was run on eight dedicated processors. (C) 2003 Elsevier Science (USA). All rights reserved.

关键词： dataflow model visual programming data processing environment automated analysis

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