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21st ACM/IEEE International Symposium on Formal Methods and Models for System Design (MEMOCODE)

作者： Theis, Daniel Schneider, Klaus RPTU Kaiserslautern Landau Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9798400703188

To ensure deterministic computations, nodes of Kahn process networks must implement sequential functions with blocking read methods. However, while the Kahn criteria are sufficient to ensure determinism, they are not necessary to ensure determinism. While it is difficult to define precise properties of nodes to ensure determinism of dataflow process networks, there are known classes of functions, such as endochronous and stable functions, that are more general than sequential functions and still ensure determinism. Endochronous functions are also of practical interest for desynchronizing systems, which is possible when a synchronous system does not react to the absence of values, so it does not need its clock and is instead triggered only by the arrival of data values. Basic nodes for defining the set of sequential functions are known. However, since the set of endochronous functions is larger than the set of sequential functions, the question arises which additional basic nodes are needed in dataflow process networks to define the endochronous functions. This paper discusses conditions that must hold for such a set of basic endochronous nodes, and presents examples of endochronous functions that must be represented in any case. In particular, we thereby focus on boolean endochronous functions so that we can reason about a finite set of functions that can be characterized by disjoint prime implicants.

关键词： dataflow process networks endochrony sequential functions

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SHeD: A Framework for Automatic Software Synthesis of Heterogeneous dataflow process networks 23

SHeD: A Framework for Automatic Software Synthesis of Hetero...

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23rd Euromicro Conference on Digital System Design (DSD)

作者： Rafique, Omair Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781728195353

A dataflow process network (DPN) is a system of concurrent processes which communicate with each other through statically determined and buffered point-to-point connections. While the general model of computation (MoC) does not impose further restrictions, many different subclasses of DPNs have been considered over time like Kahn process networks, cyclo-static networks and synchronous dataflow networks. These classes differ in the kinds of behaviors of the processes that are precisely described based on how each process is triggered for an execution, and based on how each execution of a process consumes/produces data. A heterogeneous combination of particular kinds of processes can be effectively used to model different components of a system with different kinds of MoCs. Such a composition of dataflow processes within a network is termed as heterogeneous DPN. There are design tools for modeling like Ptolemy and FERAL that support different MoCs including particular classes of DPNs by the use of so-called directors. However, design tools for synthesis are usually restricted to the weakest classes of DPNs, i.e., cyclo-static and synchronous DPNs. In this paper, we present an extendable model-based design framework called SHeD for automatic software synthesis of heterogeneous DPNs. SHeD supports different kinds of DPN processes and therefore also different kinds of MoCs. To this end, SHeD proposes a general DPN model that is used with specific definitions and constraints to formulate the precise classes of DPNs. Also, it provides a tool chain, including different specialized code generators for specific MoCs, and a runtime system that finally maps models using a combination of different MoCs on the target hardware. We demonstrate the effective use of SHeD by a case study of a distributed automotive research platform.

关键词： model-based synthesis dataflow process networks heterogeneous models of computation

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Translating Structured Sequential Programs to dataflow Graphs 21

Translating Structured Sequential Programs to Dataflow Graph...

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19th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE)

作者： Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781450391276

In this paper, a translation from structured sequential programs to equivalent dataflow process networks (DPNs) is presented that is based ,on a carefully chosen set of nodes including load/store operations to access a shared global memory. For every data structure stored in the main memory, we use corresponding tokens to enforce the sequential ordering of load/store operations accessing that data structure as far as needed Except for the load/store nodes, all nodes obey the Kahn principle so that they are deterministic in the sense that the same inputs are always mapped to the same outputs regardless of the execution schedule of the nodes. Due to the sequential ordering of load/store nodes, determinacy is also maintained by them. Moreover, the generated DPNs are quasi-static, i.e., they have schedules that are bounded in a very strict sense: For every statement of the sequential program, the corresponding DPN behaves like a homogeneous synchronous actor, i.e., it consumes one value of each input port and will finally provide one value on each output port. Hence, no more than one value needs to be stored in each buffer.

关键词： dataflow process networks Kahn process networks determinacy boundedness data races

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Synthesis of Parallel Software from Heterogeneous dataflow Models

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SN Computer Science 2022年第3期3卷 249页

作者： Rafique, Omair Schneider, Klaus Department of Computer Science University of Kaiserslautern Kaiserslautern Germany

dataflow process networks (DPNs) are intrinsically data-driven, i.e., node actions are not synchronized among each other and may fire whenever sufficient input operands arrived at a node. While the general model of computation (MoC) of DPNs does not impose further restrictions, many different subclasses of DPNs representing different dataflow MoCs have been considered over time. These classes mainly differ in the kinds of behaviors of the processes. A DPN may be heterogeneous in that different processes in the network belong to different classes of DPNs. A heterogeneous DPN can therefore be effectively used to model and to implement different components of a system with different kinds of processes and, therefore, different dataflow MoCs. This paper presents a model-based design based on different dataflow MoCs including their heterogeneous combinations. In particular, it covers the automatic software synthesis of systems from DPN models. The main objective is to validate, evaluate and compare the artifacts exhibited by different dataflow MoCs at the implementation level of systems under the supervision of a common design tool. Moreover, this work also offers an efficient synthesis method that targets and exploits heterogeneity in DPNs by generating implementations based on the kinds of behaviors of the processes. The proposed synthesis method provides a tool chain including different specialized code generators for specific dataflow MoCs, and a runtime system that finally maps models using a combination of different dataflow MoCs on cross-vendor target hardware. © 2022, The Author(s).

关键词： Automatic synthesis dataflow process networks Heterogeneity

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Efficient Handling of Arrays in dataflow process networks

Efficient Handling of Arrays in Dataflow Process Networks

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14th IEEE International Conference on High Performance Computing and Communications (HPCC) / IEEE 9th International Conference on Embedded Software and Systems (ICESS)

作者： Baudisch, Daniel Brandt, Jens Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Embedded Syst Grp D-67663 Kaiserslautern Germany

ISBN: (纸本)9780769547497

dataflow process networks (DPN) have been proposed as a programming model for distributed parallel systems that have communication paths with unpredictable latencies. The purely data-driven execution of DPNs does not require a global coordination and therefore allows one to easily map DPNs to many parallel hardware and software architectures with distributed memories. Problems due to shared memory communication like data races do not exist since the communication is done via point-to-point FIFO buffers between the process nodes. On the other hand, this distributed programming model leads to high communication costs if large data structures like arrays have to be communicated between nodes. This paper addresses the reduction of the communication costs due to arrays that are processed by - and therefore sent between - DPN nodes. The presented methods are given at a high level of abstraction and do not impose specific constraints on the used target architectures. Our experimental results show clearly the advantage of our approach compared to the standard message passing between the nodes.

关键词： arrays communication dataflow process networks DPN efficient handling

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A Formal Semantics of Exposed Datapath Architectures with Buffered processing Units 19

A Formal Semantics of Exposed Datapath Architectures with Bu...

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19th International Conference on Application of Concurrency to System Design (ACSD)

作者： Anders, Markus Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781728138435

Synchronous control asynchronous dataflow (SCAD) architectures are a new kind of exposed datapath processor architectures which reveal all of their processing units (PU) and datapaths to the compiler to increase the use of instruction-level parallelism (ILP). They employ FIFO buffers at the input and output ports of their PUs, consuming operands and producing results similar to dataflow computers. Because the arrival of operands triggers the execution of instructions, SCAD architectures only need a single type of instruction that transports data from output buffers to input buffers. Among other advantages, this allows a simple integration of application-specific PUs, since a PU may implement in principle any function that can be realized with reasonable hardware without changing the instruction set. However, simply allowing any computable function for PUs introduces problems: Because of the asynchronous nature of data moves and operation execution, not all functions yield scheduling-independent, deterministic results. In this paper, we therefore first describe an operational semantics for SCAD architectures which enables formal reasoning about the underlying model of computation. Then, we create an equivalent model using well-known dataflow process networks. From this model, the desired restrictions for functions can then be derived, giving a configurable and sound class of SCAD architectures. Finally, we discuss further restrictions that should be applied and propose a notion for well-structured SCAD machine code.

关键词： exposed data path architectures instruction-level parallelism dataflow process networks

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Toward Efficient Execution of RVC-CAL dataflow Programs on Multicore Platforms

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JOURNAL OF SIGNAL processING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2018年第11期90卷 1507-1517页

作者： Hautala, Ilkka Boutellier, Jani Nylanden, Teemu Silven, Olli Univ Oulu Dept Comp Sci & Engn Oulu Finland Tampere Univ Technol Dept Pervas Comp Tampere Finland

The increasing number of cores in System on Chips (SoC) has introduced challenges in software parallelization. As an answer to this, the dataflow programming model offers a concurrent and reusability promoting approach for describing applications. In this work, a runtime for executing dataflow process networks (DPN) on multicore platforms is proposed. The main difference between this work and existing methods is letting the operating system perform Central processing unit (CPU) load-balancing freely, instead of limiting thread migration between processing cores through CPU affinity. The proposed runtime is benchmarked on desktop and server multicore platforms using five different applications from video coding and telecommunication domains. The results show that the proposed method offers significant improvements over the state-of-art, in terms of performance and reliability.

关键词： dataflow process networks RVC-CAL Orcc Multicore

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Move Based Algorithm for Runtime Mapping of dataflow Actors on Heterogeneous MPSoCs

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JOURNAL OF SIGNAL processING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2017年第1期87卷 63-80页

作者： Thanh Dinh Ngo Martin, Kevin J. M. Diguet, Jean-Philippe Univ Bretagne Sud CNRS Ctr Rech Christiaan Huygens UMR 6285Lab STICC BP 92116 F-56100 Lorient France

Considering the evolution towards highly variable data flow applications based on an increasing impact of dynamic actors, we must target at runtime the best matching between dataflow graphs and heterogeneous multiprocessor platforms. Thus the mapping must be dynamically adapted depending on data and on communication loads between the computation cores. This is typically the case for mobile devices that run multimedia applications. The problem of mapping a dataflow application, e.g. a network of computational actors, on a multiprocessor platform can be modeled as a problem of partitioning where the cells are the dataflow actors and the partitions are the processors. While the benefit of executing a computational part by one processor rather than another one is usually well shown, the migration overhead is also usually not considered. This paper presents a dynamic mapping algorithm that is performed at runtime, based on a single-move possibility that jointly considers the cost and benefit of possible migrations. The method is first applied on a set of randomly generated benchmarks with different features and different scenarios. Then it is applied to a MPEG4 simple profile video decoder with different input sequences. The results systematically show that the runtime mapping significantly improves the initial mapping. It is fast enough to be executed at runtime in order to track the best mapping according to data variations. The other observation is that not considering the migration cost of the new mapping could lead to worst performance than the original one.

关键词： dataflow actor Heterogeneous MPSoCs Move based algorithm Runtime mapping dataflow process networks

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dataflow Model Property Verification Using Petri net Translation Techniques

Dataflow Model Property Verification Using Petri net Transla...

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9th IEEE International Conference on Industrial Informatics (INDIN)

作者： Rocha, Jose-Inacio Gomes, Luis Dias, Octavio Pascoa Escola Super Tecnol Setubal Rua Vale Chaves Setubal Portugal Univ Nova Lisboa Ctr Tecnol & Sistemas Lisbon Portugal

ISBN: (纸本)9781457704345

dataflow process networks lead to different theoretical model approaches and have demonstrated their adequacy in data-dominated intensive systems, namely Synchronous dataflows. Since their appearance, dataflow models became too focused and specialized in their target applications. The paper presents a set of translating mechanisms allowing the mapping from dataflow models into Petri nets. This mapping allows taking advantage of Petri nets well-known properties verification capabilities and enriching dataflow models concerning scheduler information and resource allocation. This allows one to find out some hidden embedded features (model semantics and syntax) not normally addressed in dataflow analysis tools, which is briefly characterized. dataflow model translation into Petri net domain give support to attain the required resource allocation under dataflow static scheduling list. This scheme allows one to make conclusion in Petri net domain to be applied in dataflow models to foresee the necessary amount of storage resources for each arc. An application example is used to illustrate the concept and effectiveness of the outlined approach.

关键词： Analytical models Biological system modeling Digital signal processing Equations Frequency domain analysis Mathematical model Petri net translation Petri nets Petri nets data flow computing data flow graphs data-dominated intensive systems dataflow model property verification dataflow process networks formal verification resource allocation resource allocation scheduler information scheduling synchronous dataflows

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