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Software Code Generation for the RVC-CAL Language

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2011年第2期63卷 203-213页

作者： Wipliez, Matthieu Roquier, Ghislain Nezan, Jean-Francois IETR INSA Rennes F-35043 Rennes France Ecole Polytech Fed Lausanne CH-1015 Lausanne Switzerland

The MPEG Reconfigurable Video Coding (RVC) framework is a new standard under development by MPEG that aims at providing a unified high-level specification of current and future MPEG video coding technologies using dataflow models. In this framework, a decoder is built as a configuration of video coding modules taken from the standard MPEG toolbox library or proprietary libraries. The elements of the library are specified by a textual description that expresses the I/O behavior of each module and by a reference software written using a subset of the CAL Actor Language named RVC-CAL. A decoder configuration is written in an XML dialect by connecting a set of CAL modules. Code generators are fundamental supports that enable the direct transformation of a high level specification to efficient hardware and software implementations. This paper presents a synthesis tool that from a CAL dataflow program generates C code and an associated SystemC model. The generated code is validated against the original CAL description simulated using the Open dataflow environment. Experimental results of the translation of two descriptions of an MPEG-4 Simple Profile decoder with different granularities are shown and discussed.

关键词： Reconfigurable Video Coding CAL actor language dataflow programming Software code generation

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Joint minimization of code and data for synchronous dataflow programs

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FORMAL METHODS IN SYSTEM DESIGN 1997年第1期11卷 41-70页

作者： Murthy, PK Bhattacharyya, SS Lee, EA UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720 HITACHI AMER LTD SEMICOND RES LABSAN JOSECA 95134

In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [21], which has been used heavily in DSP design environments over the past several years. We first focus on the restricted class of well-ordered SDF graphs. We show that while extremely efficient techniques exist for constructing minimum code size schedules for well-ordered graphs, the number of distinct minimum code size schedules increases combinatorially with the number of vertices in the input SDF graph, and these different schedules can have vastly different data memory requirements. We develop a dynamic programming algorithm that computes the schedule that minimizes the data memory requirement from among the schedules that minimize code size, and we show that the time complexity of this algorithm is cubic in the number of vertices in the given well-ordered SDF graph. We present several extensions to this dynamic programming technique to more general scheduling problems, and we present a heuristic that often computes near-optimal schedules with quadratic time complexity. We then show that finding optimal solutions for arbitrary acyclic graphs is NP-complete, and present heuristic techniques that jointly minimize code and data size requirements. We present a practical example and simulation data that demonstrate the effectiveness of these techniques.

关键词： dataflow programming synchronous dataflow memory management multirate signal processing algorithms SDF compiler on-chip memory minimum cuts dynamic programming

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Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

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SIGNAL PROCESSING-IMAGE COMMUNICATION 2013年第10期28卷 1295-1302页

作者： Yviquel, Herve Boutellier, Jani Raulet, Mickael Casseau, Emmanuel Univ Rennes 1 IRISA Inria F-35014 Rennes France IETR INSA Rennes Rennes France Univ Oulu CSE Dept SF-90100 Oulu Finland

Modern embedded systems show a clear trend towards the use of Multiprocessor System-on-Chip (MPSoC) architectures in order to handle the performance and power consumption constraints. However, the design and validation of dedicated MPSoCs is an extremely hard and expensive task due to their complexity. Thus, the development of automated design processes is of highest importance to satisfy the time-to-market pressure of embedded systems. This paper proposes an automated co-design flow based on the high-level language-based approach of the Reconfigurable Video Coding framework. The designer provides the application description in the RVC-CAL dataflow language, after which the presented co-design flow automatically generates a network of heterogeneous processors that can be synthesized on FPGA chips. The synthesized processors are Very Long Instruction Word-style processors. Such a methodology permits the rapid design of a many-core signal processing system which can take advantage of all levels of parallelism. The toolchain functionality has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to two different FPGA boards. The decoder is realized into 18 processors that decode QCIF resolution video at 45 frames per second on a 50 MHz FPGA clock frequency. The results show that the given application can take advantage of every level of parallelism. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Co-design Reconfigurable Video Coding (RVC) dataflow programming Multi-Processor System-on-Chip (MPSoC) Transport-Trigger Architecture (TTA)

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An analysis of the graph processing landscape

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JOURNAL OF BIG DATA 2021年第1期8卷 55页

作者： Coimbra, Miguel E. Francisco, Alexandre P. Veiga, Luis INESC ID R Alves Redol 9 P-1000029 Lisbon Portugal Univ Lisbon Inst Super Tecn Av Rovisco Pais 1 P-1049001 Lisbon Portugal

The value of graph-based big data can be unlocked by exploring the topology and metrics of the networks they represent, and the computational approaches to this exploration take on many forms. For the use-case of performing global computations over a graph, it is first ingested into a graph processing system from one of many digital representations. Extracting information from graphs involves processing all their elements globally, which can be done with single-machine systems (with varying approaches to hardware usage), distributed systems (either homogeneous or heterogeneous groups of machines) and systems dedicated to high-performance computing (HPC). For these systems focused on processing the bulk of graph elements, common use-cases consist in executing for example algorithms for vertex ranking or community detection, which produce insights on graph structure and relevance of their elements. Many distributed systems (such as Flink, Spark) and libraries (e.g. Gelly, GraphX) have been built to enable these tasks and improve performance. This is achieved with techniques ranging from classic load balancing (often geared to reduce communication overhead) to exploring trade-offs between delaying computation and relaxing accuracy. In this survey we firstly familiarize the reader with common graph datasets and applications in the world of today. We provide an overview of different aspects of the graph processing landscape and describe classes of systems based on a set of dimensions we describe. The dimensions we detail encompass paradigms to express graph processing, different types of systems to use, coordination and communication models in distributed graph processing, partitioning techniques and different definitions related to the potential for a graph to be updated. This survey is aimed at both the experienced software engineer or researcher as well as the graduate student looking for an understanding of the landscape of solutions (and their limitations) for graph

关键词： Graph processing Distributed systems Online processing Graph representation dataflow programming

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LLVM-based and scalable MPEG-RVC decoder

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JOURNAL OF REAL-TIME IMAGE PROCESSING 2011年第1期6卷 59-70页

作者： Gorin, Jerome Wipliez, Matthieu Preteux, Francoise Raulet, Mickael INSA Rennes IETR F-35043 Rennes France Inst Telecom SudParis ARTEMIS UMR 8145 Evry France

MPEG reconfigurable video coding (RVC) is a new platform-independent specification methodology chosen by the MPEG community for describing coding standards. This methodology aims at producing abstract decoder models (ADMs) of MPEG decoders as programs described in a dataflow language namely "RVC-CAL Actor Language" (RVC-CAL). RVC-CAL naturally expresses potential parallelism between tasks of an application, which makes an ADM description suitable for implementation to a wide variety of platforms, from uniprocessor systems to FPGAs. MPEG RVC eases the development process of decoders by building decoders at a library-component level instead of using monolithic algorithms, and by providing a library of coding tools standardized in MPEG. This paper presents new mechanisms based on the low level virtual machine that allow the conception of a decoder able to dynamically instantiate several RVC decoder descriptions. This decoder, unlike static decoders generated by RVC tools, keeps de facto the features of an RVC description namely portability, scalability and reconfigurability.

关键词： Reconfigurable video coding RVC-CAL actor language Low level virtual machine Network scheduling dataflow programming Code synthesis Multi-core systems

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MPEG Reconfigurable Video Coding: From specification to a reconfigurable implementation

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SIGNAL PROCESSING-IMAGE COMMUNICATION 2013年第10期28卷 1224-1238页

作者： Gorin, Jerome Raulet, Mickael Preteux, Francoise TELECOM ParisTech UMR 5141 F-75013 Paris France INSA Rennes IETR F-35000 Rennes France MINES ParisTech F-75272 Paris France

This paper demonstrates that it is possible to produce automatic, reconfigurable, and portable implementations of multimedia decoders onto platforms with the help of the MPEG Reconfigurable Video Coding (RVC) standard. MPEG RVC is a new formalism standardized by the MPEG consortium used to specify multimedia decoders. It produces visual representations of decoder reference software, with the help of graphs that connect several coding tools from MPEG standards. The approach developed in this paper draws on dataflow Process Networks to produce a Minimal and Canonical Representation (MCR) of MPEG RVC specifications. The MCR makes it possible to form automatic and reconfigurable implementations of decoders which can match any actual platforms. The contribution is demonstrated on one case study where a generic decoder needs to process a multimedia content with the help of the RVC specification of the decoder required to process it. The overall approach is tested on two decoders from MPEG, namely MPEG-4 part 2 Simple Profile and MPEG-4 part 10 Constrained Baseline Profile. The results validate the following benefits on the MCR of decoders: compact representation, low overhead induced by its compilation, reconfiguration and multi-core abilities. (C) 2013 Elsevier B.V. All rights reserved.

关键词： MPEG Reconfigurable Video Coding dataflow programming RVC-CAL Actor Language LLVM

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Methods to explore design space for MPEG RMC codec specifications

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SIGNAL PROCESSING-IMAGE COMMUNICATION 2013年第10期28卷 1278-1294页

作者： Casale-Brunet, Simone Elguindy, Abdallah Bezati, Endri Thavot, Richard Roquier, Ghislain Mattavelli, Marco Janneck, Jorn W. Ecole Polytech Fed Lausanne CH-1015 Lausanne Switzerland Lund Univ Dept Comp Sci S-22100 Lund Sweden

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementation on specific targets. To this end, the RMC framework has standardized both an asynchronous dataflow model of computation and an associated specification language. Either are providing the formalism and the theoretical foundation for multimedia specifications. Even though these specifications are abstract and platform-independent the new approach of developing implementations from such initial specifications presents obvious advantages over the approaches based on classical sequential specifications. The advantages appear particularly appealing when targeting the current and emerging homogeneous and heterogeneous manycore or multicore processing platforms. These highly parallel computing machines are gradually replacing single-core processors, particularly when the system design aims at reducing power dissipation or at increasing throughput However, a straightforward mapping of an abstract dataflow specification onto a concurrent and heterogeneous platform does often not produce an efficient result Before an abstract specification can be translated into an efficient implementation in software and hardware, the dataflow networks need to be partitioned and then mapped to individual processing elements. Moreover, system performance requirements need to be accounted for in the design optimization process. This paper discusses the state of the art of the combinatorial problems that need to be faced at this design space exploration step. Some recent developments and experimental results for image and video coding applications are illustrated. Both well-known and novel heuristics for problems such as mapping, scheduling and buffer minimization are investigated in the specific context of exploring the design space of dat

关键词： Reconfigurable Media Coding Design space exploration Parallel computing dataflow programming Parallel Analysis and Optimization

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APGAN and RPMC: Complementary heuristics for translating DSP block diagrams into efficient software implementations

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 1997年第1期2卷 33-60页

作者： Bhattacharyya, SS Murthy, PK Lee, EA UNIV CALIF BERKELEY DEPT ELECT ENGN & COMP SCIBERKELEYCA 94720

dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly well-suited to dataflow-based graphical programming because its restricted semantics offer strong formal properties and significant compile-time predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations. We consider two approaches. The first is a customization to acyclic graphs of a bottom-up technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier for general SDF graphs. We show that our customization to acyclic graphs significantly reduces the complexity of the general PGAN algorithm, and we present a formal study of our modified PGAN technique that rigorously establishes its optimality for a certain class of applications. The second approach that we consider is a top-down technique, based on a generalized minimum-cut operation, that was introduced recently in [14]. We present the results of an extensive experimental investigation on the performance of our modified PGAN technique and the top-down approach and on the tradeoffs between them. Based on these results, we conclude that these two techniques complement each other, and thus, they should both be incorporated into SDF-based software implementation environments in which the minimization of memory requirements is important. We have implemented these algorithms in the Ptolemy software environment [5] at UC Berkeley.

关键词： dataflow programming synchronous dataflow memory management multirate signal processing algorithms SDF compiler on-chip memory clustering minimum cuts dynamic programming

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Embedded Multi-Core Systems Dedicated to Dynamic dataflow Programs

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2015年第1期80卷 121-136页

作者： Yviquel, Herve Sanchez, Alexandre Jaaskelainen, Pekka Takala, Jarmo Raulet, Mickael Casseau, Emmanuel INSA Rennes IETR Rennes France Tampere Univ Technol FIN-33101 Tampere Finland Univ Rennes 1 IRISA Inria Rennes France

Multimedia applications and embedded platforms are both becoming very complex in order to improve user experience. Thus, multimedia developers need high-level methods to automate time-consuming and error-prone tasks. Dynamic dataflow modeling is attractive to describe complex applications, such as video codecs, at a high level of abstraction. This paper presents a dataflow-based design approach to implement video codecs on embedded multi-core platforms. First, we introduce a custom architecture model to design low-power multi-core chips based on distributed memory and Transport-Triggered Architecture processor cores. Then, we describe software synthesis techniques to improve dynamic dataflow implementations. This methodology has been implemented into open-source tools and demonstrated on video decoders based on the MPEG-4 Visual standard and the new High Efficiency Video Coding standard. The simulations achieve real-time decoding (40FPS) of high definition (720P) MPEG-4 Visual video sequences on a custom multi-core platform clocked at 1Ghz, which is an improvement of more than 100 % over previously proposed implementations.

关键词： dataflow programming Video coding HEVC Embedded system

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Topology-Aware and Dependence-Aware Scheduling and Memory Allocation for Task-Parallel Languages

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ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 2014年第3期11卷 181-205页

作者： Drebes, Andi Pop, Antoniu Heydemann, Karine Cohen, Albert Drach, Nathalie Univ Manchester Sch Comp Sci Manchester M13 9PL Lancs England Ecole Normale Super Dept Informat F-75005 Paris France UPMC Univ Paris 06 Sorbonne Univ CNRS UMR 7606LIP6 Paris France Ecole Normale Super F-75005 Paris France INRIA Le Chesnay France

We present a joint scheduling and memory allocation algorithm for efficient execution of task-parallel programs on non-uniform memory architecture (NUMA) systems. Task and data placement decisions are based on a static description of the memory hierarchy and on runtime information about intertask communication. Existing locality-aware scheduling strategies for fine-grained tasks have strong limitations: they are specific to some class of machines or applications, they do not handle task dependences, they require manual program annotations, or they rely on fragile profiling schemes. By contrast, our solution makes no assumption on the structure of programs or on the layout of data in memory. Experimental results, based on the Open-Stream language, show that locality of accesses to main memory of scientific applications can be increased significantly on a 64-core machine, resulting in a speedup of up to 1.63x compared to a state-of-the-art work-stealing scheduler.

关键词： Performance Languages FIFO queue dynamic scheduling work stealing lock-free algorithm weak memory model dataflow programming Kahn process network

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