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Fairness in dataflow scheduling in the cloud

INFORMATION SYSTEMS 2019年 83卷 118-125页

作者： Pietri, Ilia Chronis, Yannis Ioannidis, Yannis Univ Athens Dept Informat & Telecommun Athens Greece Univ Wisconsin Madison Comp Sci Dept Madison WI USA Athena Res Ctr Maroussi Greece Intracom SA Telecom Solut Paiania Greece

Expensive dataflow queries which may involve large-scale computations operating on significant volumes of data are typically executed on distributed platforms to improve application performance. Among these, cloud computing has emerged as an attractive option for users to execute dataflows allowing them to select proper configurations (e.g., number of machines) to achieve desired trade-offs between execution time and monetary cost. Discovering dataflow schedules that exhibit the best trade-offs within a plethora of potential solutions can be challenging, especially in a heterogeneous environment where resource characteristics like performance and price can be varied. To increase resource utilization, users may also submit multiple dataflows for execution concurrently. Traditionally, building fair schedules (schedules where the slowdown of all dataflows due to resource sharing is similar) while achieving good performance is a major concern. However, considering fairness in the cloud computing setting where monetary cost is part of the optimization objectives significantly increases the difficulty of the scheduling problem. This paper proposes an algorithm for the scheduling of multiple dataflows on heterogeneous clouds that identifies Pareto-optimal solutions (schedules) in the three-dimensional space formed from the different trade-offs between overall execution time, monetary cost and fairness. The results show that in most cases the proposed approach can provide solutions with fairer schedules without significantly impacting the quality of the execution time to monetary cost skyline compared to the state of the art where the fairness of a solution is not taken into account. (C) 2019 Elsevier Ltd. All rights reserved.

关键词： Cloud computing Multiple dataflows Fairness dataflow scheduling

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scheduling optimization for upstream dataflows in edge computing

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Digital Communications and Networks 2023年第6期9卷 1448-1457页

作者： Haohao Wang Mengmeng Sun Lianming Zhang Pingping Dong Yehua Wei Jing Mei College of Information Science and Engineering Hunan Normal UniversityChangsha410081China Hunan Provincial Key Laboratory of Intelligent Computing and Language Information Processing Hunan Normal UniversityChangsha410081China Hunan Xiangjiang Artificial Intelligence Academy Hunan Normal UniversityChangsha410081China

Edge computing can alleviate the problem of insufficient computational resources for the user equipment,improve the network processing environment,and promote the user *** computing is well known as a prospective method for the development of the Internet of Things(IoT).However,with the development of smart terminals,much more time is required for scheduling the terminal high-intensity upstream dataflow in the edge server than for scheduling that in the downstream *** this paper,we study the scheduling strategy for upstream dataflows in edge computing networks and introduce a three-tier edge computing network *** propose a Time-Slicing Self-Adaptive scheduling(TSAS)algorithm based on the hierarchical queue,which can reduce the queuing delay of the dataflow,improve the timeliness of dataflow processing and achieve an efficient and reasonable performance of dataflow *** experimental results show that the TSAS algorithm can reduce latency,minimize energy consumption,and increase system throughput.

关键词： Edge computing Time-slicing dataflow scheduling Dynamic analysis

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Data-Driven Thread Execution on Heterogeneous Processors

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INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING 2018年第2期46卷 198-224页

作者： Arandi, Samer Matheou, George Kyriacou, Costas Evripidou, Paraskevas An Najah Natl Univ Dept Comp Engn Nablus Palestine Univ Cyprus Dept Comp Sci Nicosia Cyprus Frederick Univ Dept Comp Sci & Engn Nicosia Cyprus

In this paper we report our experience in implementing and evaluating the Data-Driven Multithreading (DDM) model on a heterogeneous multi-core processor. DDM is a non-blocking multithreading model that decouples the synchronization from the computation portions of a program, allowing them to execute asynchronously in a dataflow manner. Thread dependencies are determined by the compiler/programmer while thread scheduling is done dynamically at runtime based on data availability. The target processor for this implementation is the Cell processor. We call this implementation the Data-Driven Multithreading Virtual Machine for the Cell processor (DDM-). Thread scheduling is handled in software by the Power Processing Element core of the Cell while the Synergistic Processing Element cores execute the program threads. DDM- virtualizes the parallel resources of the Cell, handles the heterogeneity of the cores, manages the Cell memory hierarchy efficiently and supports distributed execution across a cluster of Cell nodes. DDM- has been implemented on a single Cell processor with six computation cores, as well as, on a four Cell processor cluster with 24 computation cores. We present an in-depth performance analysis of DDM-, using a suite of standard computational benchmarks. The evaluation shows that DDM- scales well and tolerates scheduling overheads, memory and communication latencies effectively. Furthermore, DDM- compares favorably with other platforms targeting the Cell processor, such as, the CellSs and Sequoia.

关键词： Multi-core systems Data-Driven Multithreading dataflow scheduling CacheFlow

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Toward efficient neural architecture search with dynamic mapping-adaptive sampling for resource-limited edge device

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NEURAL COMPUTING & APPLICATIONS 2023年第7期35卷 5553-5573页

作者： Yang, Zhao Sun, Qingshuang Northwestern Polytech Univ Sch Comp Sci 1 Dongxiang Rd Xian 710129 Shaanxi Peoples R China

To account for both network accuracy and deployment efficiency, multi-objective NAS has been proposed. However, these methods are still inefficient. As a result of the previous coarse-grained performance descriptions, the acquisition of feasible networks is limited, reducing the effectiveness and efficiency of search direction updates. As a consequence, a large number of ineffective network structures that do not meet the application requirements are sampled and trained, significantly reducing search efficiency. To address the two issues, this paper uses adaptive dataflow mapping to describe the inference latency of the sampled network structures in a fine-grained manner, thereby expanding the search space of available networks. The sampling behavior is dynamically adjusted in accordance with the system latency requirement and the allocable latency for each layer. The sampled network structure's latency will approach the system requirement. Finally, by reducing the number of infeasible networks, search efficiency is improved. Experiments show that comparing state-of-the-art methods, the accuracy of the networks searched by our framework can be improved by up to 7.93% while meeting specific inference latency requirements. However, search efficiency can be improved up to 2.35x.

关键词： NAS Hardware-aware Inference latency dataflow scheduling Dynamic sampling

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Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management

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MICROPROCESSORS AND MICROSYSTEMS 2013年第8期37卷 1090-1101页

作者： Poss, R. Lankamp, M. Yang, Q. Fu, J. van Tol, M. W. Uddin, I. Jesshope, C. Univ Amsterdam NL-1098 XH Amsterdam Netherlands

To harness the potential of CMPs for scalable, energy-efficient performance in general-purpose computers, the Apple-CORE project has co-designed a general machine model and concurrency control interface with dedicated hardware support for concurrency management across multiple cores. Its SVP interface combines dataflow synchronisation with imperative programming, towards the efficient use of parallelism in general-purpose workloads. Its implementation in hardware provides logic able to coordinate single-issue, in-order multi-threaded RISC cores into computation clusters on chip, called Microgrids. In contrast with the traditional "accelerator" approach, Microgrids are components in distributed systems on chip that consider both clusters of small cores and optional, larger sequential cores as system services shared between applications. The key aspects of the design are asynchrony, i.e. the ability to tolerate irregular long latencies on chip, a scale-invariant programming model, a distributed chip resource model, and the transparent performance scaling of a single program binary code across multiple cluster sizes. This article describes the execution model, the core micro-architecture, its realization in a many-core, general-purpose processor chip and its software environment. This article also presents cycle-accurate simulation results for various key algorithmic and cryptographic kernels. The results show good efficiency in terms of the utilisation of hardware despite the high-latency memory accesses and good scalability across relatively large clusters of cores. (C) 2013 Elsevier B.V. All rights reserved.

关键词： Chip multiprocessors Many-cores Hardware multithreading dataflow scheduling Operating systems in hardware Microgrids

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DCNN search and accelerator co-design: Improve the adaptability between NAS frameworks and embedded platforms

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INTEGRATION-THE VLSI JOURNAL 2022年 87卷 147-157页

作者： Li, Chuxi Fan, Xiaoya Zhang, Shengbing Yang, Zhao Wang, Miao Wang, Danghui Zhang, Meng Northwestern Polytech Univ Sch Comp Sci Minist Educ Engn Res Ctr Embedded Syst Integrat Xian Peoples R China

The gap between Neural Architecture Search (NAS) and hardware embedded accelerators degrades the deployment efficiency, due to the absent of rethinking the applicability of the searched network layer characteristics and hardware mapping. Therefore, this work proposes a novel hardware-aware NAS framework in consideration of a deduced efficiency metric. Beside, a layer adaptive scheduler and a coarse-grained reconfigurable computing architecture are developed to deploy the searched networks by selecting the most appropriate dataflow pattern layer-by-layer. Evaluation results show that the proposed NAS framework can search networks with high accuracy and low inference latency, and the proposed architecture provides power-efficiency

关键词： Deep Convolutional Neural Network Neural Architecture Search Hardware-aware dataflow scheduling Embedded accelerator

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Optimized dynamic compilation of dataflow representations for multimedia applications

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ANNALS OF TELECOMMUNICATIONS 2013年第3-4期68卷 133-151页

作者： Gorin, Jerome Raulet, Mickael Preteux, Francoise Inst Telecom SudParis ARTEMIS UMR Evry France INSA Rennes IETR F-35043 Rennes France MINES ParisTech F-75272 Paris France

This paper proposes two optimization methods based on dataflow representations and dynamic compilation that enhance flexibility and performance of multimedia applications. These optimization methods are intended to be used in an adaptive decoding context, or, in other terms, where decoders have the ability to adapt their decoding processes according to a bitstream. This adaptation is made possible by coupling the decoding information to process a stream inside a coded stream. In this paper, we use dataflow representations from the upcoming MPEG Reconfigurable Media Coding (RMC) standard to supply the decoding information to adaptive decoders. The benefits claimed by MPEG RMC are a reuse of coding tools between different specifications of decoder and an execution scalability on different processing units with a single specification, which can target either hardware and/or software platforms. These benefits are not yet achievable in practice as these specifications are not used at the receiver side in MPEG RMC. We valid these benefits and propose two optimizations for the generation and the execution of dataflow models: the first optimization takes benefits of the reuse of coding tools to reduce the time to obtain-configure-enforceable decoders. The second provides an efficient, dynamic, and scalable execution according to the features of the execution platform. We show the practical impact of these two optimizations on two decoder representations compliant with the MPEG-4 part 2 Simple Profile standard and the MPEG-4 Advanced Video Coding standard. The results shows that configuration time can be reduced by 3 and the performance of decoders can be increased by 50 %.

关键词： MPEG reconfigurable media coding MPEG reconfigurable video coding MPEG reconfigurable graphic coding Dynamic compilation Adaptive decoding Multimedia application dataflow program Reconfiguration Scalable execution dataflow process network dataflow scheduling

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Enhancing Graph Random Walk Acceleration via Efficient dataflow and Hybrid Memory Architecture

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IEEE TRANSACTIONS ON COMPUTERS 2024年第3期73卷 887-901页

作者： Gao, Yingxue Wang, Teng Gong, Lei Wang, Chao Hu, Yiqing Yang, Yi Liu, Zhongming Li, Xi Zhou, Xuehai Univ Sci & Technol China Hefei 230026 Anhui Peoples R China Univ Sci & Technol China Suzhou Inst Adv Res Suzhou 215123 Peoples R China Changxin Memory Technol Hefei 230000 Anhui Peoples R China

Graph random walk sampling is becoming increasingly important with the widespread popularity of graph applications. It aims to capture the desirable graph properties by launching multiple walkers to collect feature paths. However, previous research suffers long sampling latency and severe memory access bottlenecks due to intrinsic data dependency and skewed vertex distribution. Thus, in this paper, we propose FastRW, a dedicated accelerator to boost graph random walk operation on FPGAs. Specifically, FastRW first integrates multiple parallel processing engines to achieve data-level parallelism, where each processing engine also leverages dataflow scheduling to resolve data dependency and hide long sampling latency. Secondly, FastRW leverages a combination of multiple storage resources to implement a hybrid memory architecture adapted to skewed vertex distribution. By integrating the above optimizations, FastRW develops a performance model to take advantage of the balance between computation parallelism and bandwidth demand. We evaluate FastRW with two classic sampling algorithms on a wide range of real-world graph datasets. The experimental results show that FastRW achieves a speedup of 37.52x on average over the system running on two 8-core Intel CPUs. FastRW also achieves an average of 28.04x speedup over the architecture implemented on V100 GPU.

关键词： Parallel processing Sampling methods Computer architecture Field programmable gate arrays Pipelines Memory architecture Engines Graph random walk dedicated accelerator dataflow scheduling hybrid memory architecture

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TETRIS: Scalable and Efficient Neural Network Acceleration with 3D Memory 17

TETRIS: Scalable and Efficient Neural Network Acceleration w...

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22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

作者： Gao, Mingyu Pu, Jing Yang, Xuan Horowitz, Mark Kozyrakis, Christos Stanford Univ Stanford CA 94305 USA

ISBN: (纸本)9781450344654

The high accuracy of deep neural networks (NNs) has led to the development of NN accelerators that improve performance by two orders of magnitude. However, scaling these accelerators for higher performance with increasingly larger NNs exacerbates the cost and energy overheads of their memory systems, including the on-chip SRAM buffers and the off-chip DRAM channels. This paper presents the hardware architecture and software scheduling and partitioning techniques for TETRIS, a scalable NN accelerator using 3D memory. First, we show that the high throughput and low energy characteristics of 3D memory allow us to rebalance the NN accelerator design, using more area for processing elements and less area for SRAM buffers. Second, we move portions of the NN computations close to the DRAM banks to decrease bandwidth pressure and increase performance and energy efficiency. Third, we show that despite the use of small SRAM buffers, the presence of 3D memory simplifies dataflow scheduling for NN computations. We present an analytical scheduling scheme that matches the efficiency of schedules derived through exhaustive search. Finally, we develop a hybrid partitioning scheme that parallelizes the NN computations over multiple accelerators. Overall, we show that TETRIS improves the performance by 4.1x and reduces the energy by 1.5x over NN accelerators with conventional, low-power DRAM memory systems.

关键词： 3D memory neural networks acceleration dataflow scheduling partitioning

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Hardware-Aware NAS Framework with Layer Adaptive scheduling on Embedded System 21

Hardware-Aware NAS Framework with Layer Adaptive Scheduling ...

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26th Asia and South Pacific Design Automation Conference (ASP-DAC)

作者： Li, Chuxi Fan, Xiaoya Zhang, Shengbing Yang, Zhao Wang, Miao Wang, Danghui Zhang, Meng Northwestern Polytech Univ Minist Educ Sch Comp Sci Engn Res Ctr Embedded Syst Integrat Xian Peoples R China Northwestern Polytech Univ Sch Comp Sci Xian Peoples R China

ISBN: (纸本)9781450379991

Neural Architecture Search (NAS) has been proven to be an effective solution for building Deep Convolutional Neural Network (DCNN) models automatically. Subsequently, several hardware-aware NAS frameworks incorporate hardware latency into the search objectives to avoid the potential risk that the searched network cannot be deployed on target platforms. However, the mismatch between NAS and hardware persists due to the absent of rethinking the applicability of the searched network layer characteristics and hardware mapping. A convolution neural network layer can be executed on various dataflows of hardware with different performance, with which the characteristics of on-chip data using varies to fit the parallel structure. This mismatch also results in significant performance degradation for some maladaptive layers obtained from NAS, which might achieved a much better latency when the adopted dataflow changes. To address the issue that the network latency is insufficient to evaluate the deployment efficiency, this paper proposes a novel hardware-aware NAS framework in consideration of the adaptability between layers and dataflow patterns. Beside, we develop an optimized layer adaptive data scheduling strategy as well as a coarse-grained reconfigurable computing architecture so as to deploy the searched networks with high power-efficiency by selecting the most appropriate dataflow pattern layer-by-layer under limited resources. Evaluation results show that the proposed NAS framework can search DCNNs with the similar accuracy to the state-of-the-art ones as well as the low inference latency, and the proposed architecture provides both power-efficiency improvement and energy consumption saving.

关键词： neural netwoks NAS hardware-aware dataflow scheduling embedded system

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