The flight data recorder continually logs memory races in a multithreaded execution, enabling the deterministic replay invaluable for debugging concurrency errors, yet adds only modest hardware to a multicore chip. In...
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The flight data recorder continually logs memory races in a multithreaded execution, enabling the deterministic replay invaluable for debugging concurrency errors, yet adds only modest hardware to a multicore chip. In experiments, recording incurred less than 2 percent runtime overhead.
The branch misprediction penalty is a major performance limiter and a major cause of wasted energy in high-performance processors. The diverge-merge processor reduces this penalty by dynamically predicating a wide ran...
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The branch misprediction penalty is a major performance limiter and a major cause of wasted energy in high-performance processors. The diverge-merge processor reduces this penalty by dynamically predicating a wide range of hard-to-predict branches at runtime in an energy-efficient way that doesn't significantly increase hardware complexity or require major ISA changes.
Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected...
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Equipping processors with programmable hardware to patch design errors lets manufacturers release regular hardware patches, avoiding costly chip recalls and potentially speeding time to market. For each error detected, the manufacturer creates a fingerprint, which the customer uses to program the hardware. The hardware watches for error conditions;when they arise, it takes action to avoid the error.
Software reliability is one of important characteristics of software quality, and software release time is an important application of the software reliability model. In this article we consider a software release pol...
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Software reliability is one of important characteristics of software quality, and software release time is an important application of the software reliability model. In this article we consider a software release policy based on a Gamma-Gamma-type Kalman filter as well as the risk cost due to software failures and the cost for debugging in software systems. Under this model, the optimal release time that minimizes the expected cost in every test-debugging stage subject to a reliability constraint is discussed. An example to illustrate the framework of our model is given.
This article proposes an innovative concurrent-program invariant that captures programmers' atomicity assumptions. It describes a tool with two implementations, one in software and the other using hardware support...
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This article proposes an innovative concurrent-program invariant that captures programmers' atomicity assumptions. It describes a tool with two implementations, one in software and the other using hardware support, that can automatically extract such invariants and detect atomicity violation bugs.
Software-only reliability techniques protect against transient faults without the overhead of hardware techniques. Although existing low-level software- only fault-tolerance techniques detect faults, they offer no rec...
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Software-only reliability techniques protect against transient faults without the overhead of hardware techniques. Although existing low-level software- only fault-tolerance techniques detect faults, they offer no recovery assistance. This article describes three automatic, instruction-level, software- only recovery techniques representing different trade-offs between reliability and performance.
Embedded systems are increasingly pervasive, and the creation of reliable controlling software offers unique challenges. Embedded software must interact directly with hardware, it must respond to events in a time-crit...
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Embedded systems are increasingly pervasive, and the creation of reliable controlling software offers unique challenges. Embedded software must interact directly with hardware, it must respond to events in a time-critical fashion, and it typically employs concurrency to meet response time requirements. This paper describes an innovative course that gives students in-depth exposure to the challenges of writing reliable, time-critical, concurrent code. Students design and implement a real-time operating system (RTOS), and they write application code that uses the RTOS they construct. Code development and debugging take place in a simulation environment that offers visibility into the system and strictly repeatable execution while maintaining hardware compatibility. We describe the structure of the class, the custom tools used, and the laboratory sequence that results in a functional RTOS. We discuss the development of the class and its impact on our students.
In the 1970s, around the time that MOS Technology introduced the 8-bit 6502processor, I took a job as chief engineer at a company that developed, manufactured, and suppliedmilitary and industrial security-monitoring s...
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In the 1970s, around the time that MOS Technology introduced the 8-bit 6502processor, I took a job as chief engineer at a company that developed, manufactured, and suppliedmilitary and industrial security-monitoring systems. Job 1 was an intermittent problem in thecurrent model that caused the watchdog timer to reset the system. The default condition for a systemreset was to secure all doors and sensors throughout the monitored areas to condition "red."
debugging EMBEDDED SYSTEMS CAM REPRESENT MORE THAN HALF OF ANEMBEDDED-SOFTWARE-PROJECT WORKLOAD. UNDERSTANDING HARDWARE-debugging FUNCTIONS AND THE ISSUES THEYTACKLE IS KEY TO SELECTING THE RIGHT CHIPS, BUILDING DEBUG...
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debugging EMBEDDED SYSTEMS CAM REPRESENT MORE THAN HALF OF ANEMBEDDED-SOFTWARE-PROJECT WORKLOAD. UNDERSTANDING HARDWARE-debugging FUNCTIONS AND THE ISSUES THEYTACKLE IS KEY TO SELECTING THE RIGHT CHIPS, BUILDING debugging SYSTEMS, AND INCREASING *** people erroneously credit the term 'bug' to Rear Admiral Grace Murray Hopper. In fact,however, no one knows where the term originated, and it may go back to Thomas A Edison or evenearlier. Nevertheless, US Naval Reservist Hopper found a moth that had short-circuited Relay #70,Panel F, of the Mark II Aiken Relay Calculator while it was being tested at Harvard University onSept 9,1945. By removing the moth - that is, 'debugging' the computer, she solved the glitch thathad temporarily shut down the machine (Reference 1). Although that early example literally removed abug from a system's hardware, 'debugging' today refers to the process of understanding a programfailure and removing the defective code. A failure includes any small deviation from the originalintention, and removing the defective code is much better than adding correction code. In an idealsituation, all characteristics, such as bus and register values of a system, would be accessible atany time for monitoring and modification. But with ICs moving toward SOCs (systems on chips),accessibility becomes more difficult.
The introduction of complex systems-on-chip (SoC) devices with multiple processor cores presents new challenges for embedded systems developers. Novel development tools specifically targeting complex SoC will help ove...
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The introduction of complex systems-on-chip (SoC) devices with multiple processor cores presents new challenges for embedded systems developers. Novel development tools specifically targeting complex SoC will help overcome these challenges, but are typically limited by inadequate debug support facilities within the SoC. High-quality debug support with advanced features is essential to take full advantage of complex SoC devices in challenging applications while simultaneously reducing development time. Here, existing strategies for providing comprehensive SoC debug support targeting hard real-time applications, such as automotive control, where development challenges are overwhelming are reviewed. This overview includes an evaluation of the available solutions and their suitability for use with the next generation of complex SoC based on multiple processor cores. It is shown that many existing solutions do not readily pen-nit developers to take advantage of the complex features integrated into the next generation of SoC. The essential features of debug support for multiple processor core SoCs are summarised and discussed. Recommendations are made for SoC designers and for the future direction of research in this area, with the aim of providing a more suitable foundation for new development tools. Such tools are badly needed for all hard real-time embedded systems and are paramount to managing the development complexity introduced by SoC devices with multiple highly interactive processor cores and active peripherals.
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