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7th IEEE International Conference on Computational Intelligence and Computing Research (ICCIC)

作者： Yedere, Naveen Kumar Pamula, Vinay Kumar JNTUK Univ Coll Engn Dept ECE Kakinada 533003 India

ISBN: (纸本)9781509006120

This paper presents a method of increasing reliability of memory, so as not to make the data erroneous, and to make the data free from multiple cell upsets (MCUs). There are many methods to increase the reliability of memory, but in this paper a modification to decimal matrix code is proposed with reduced redundant bits. The error correction codes which are used to protect memories and to increase the reliability of memory are more complex, because of the shrinking of CMOS technology. The proposed technique increases error detection capability due to the use of decimal algorithm. In the existing decimal matrix code there are more number of redundant bits, which are required for the detection and correction of the data in the memory. In this paper same algorithm as that of decimal matrix code is used but, the number of redundant bits are reduced and it also has less area and power.

关键词： Multiple cell upsets (MCUs) decimal algorithm error correction codes memory

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Low Overhead decimal Matrix Code with Dynamic Network on Chip against Multiple Cell Upsets 2

Low Overhead Decimal Matrix Code with Dynamic Network on Chi...

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2015 International Conference on Innovations in Information, Embedded and Communication Systems (ICIIECS)

作者： Anitha, B. Jeevidha, B. Mookambigai Coll Engn VLSI Design Pudukkottai Tamil Nadu India Mookambigai Coll Engn Pudukkottai Tamil Nadu India

ISBN: (纸本)9781479968183

This paper presents an efficient decimal matrix code (DMC) technique to obtain the maximum error detection capability. This model can minimize the area overhead of extra circuits using encoder reusing technique (ERT). To maintain the reliability of memories against transient multiple cell upsets decimal matrix code based on divide-symbol is presented. Also the DMC mechanism is suitable for dynamic NOCs where the number and position of processor elements or faulty blocks vary during runtime. Here we present a NOC based on online error detection mechanism and adaptive routing algorithm. NoC is based on routers performing online error detection of routing algorithm and data packet errors. Adaptive routing algorithm allows to bypass faulty components or processor elements dynamically implemented inside the network. The new router architecture is based on additional diagonal state indications and specific logic blocks allowing the reliable operation of the NoC. The main originality in the NoC is that only the permanently faulty parts of the routers are disconnected. Therefore, it maintains a high run time throughput in the NoC without data packet due to self-loopback mechanism inside each router.

关键词： decimal algorithm Adaptive algorithm Dynamic reconfiguration Memory Multiple cells upsets (MCUs) Network-on-chip (NoC) Reliability Error correction codes (ECCs)

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Enhanced Memory Reliability Against Multiple Cell Upsets Using decimal Matrix Code

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2014年第1期22卷 127-135页

作者： Guo, Jing Xiao, Liyi Mao, Zhigang Zhao, Qiang Harbin Inst Technol Microelect Ctr Harbin 150001 Peoples R China

Transient multiple cell upsets (MCUs) are becoming major issues in the reliability of memories exposed to radiation environment. To prevent MCUs from causing data corruption, more complex error correction codes (ECCs) are widely used to protect memory, but the main problem is that they would require higher delay overhead. Recently, matrix codes (MCs) based on Hamming codes have been proposed for memory protection. The main issue is that they are double error correction codes and the error correction capabilities are not improved in all cases. In this paper, novel decimal matrix code (DMC) based on divide-symbol is proposed to enhance memory reliability with lower delay overhead. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Moreover, the encoder-reuse technique (ERT) is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. ERT uses DMC encoder itself to be part of the decoder. The proposed DMC is compared to well-known codes such as the existing Hamming, MCs, and punctured difference set (PDS) codes. The obtained results show that the mean time to failure (MTTF) of the proposed scheme is 452.9%, 154.6%, and 122.6% of Hamming, MC, and PDS, respectively. At the same time, the delay overhead of the proposed scheme is 73.1%, 69.0%, and 26.2% of Hamming, MC, and PDS, respectively. The only drawback to the proposed scheme is that it requires more redundant bits for memory protection.

关键词： decimal algorithm error correction codes (ECCs) mean time to failure (MTTF) memory multiple cells upsets (MCUs)

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