检索结果-内蒙古大学图书馆

Complexity Analysis of an HEVC decoder based on a Digital Signal Processor

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2013年第2期59卷 391-399页

作者： Pescador, F. Chavarrias, M. Garrido, M. J. Juarez, E. Sanz, C. Univ Politecn Madrid Ctr SW Technol & Multimedia Syst CITSEM E-28040 Madrid Spain

High Efficiency Video Coding (HEVC) is a new video coding standard created by the JCT-VC group within ISO/IEC and ITU-T. HEVC is targeted to provide the same quality as H. 264 at about half of the bit-rate and will replace soon to its predecessor in multimedia consumer applications. Up to now, only a few decoder implementations have been reported, most of them oriented to carry out a complexity analysis. In this paper, a DSP-based implementation of the HEVC HM9.0 decoder is presented. Up to the best of our knowledge, it is the first DSP-based implementation shown in the scientific literature. Several tests have been carried out to measure the decoder performance and the computational load distribution among its functional blocks. These results have been compared with the ones obtained with the decoder implementations reported up to date. Finally, based on the results obtained in previous works regarding software optimization of DSP-based decoders, real-time could be achieved for SD formats with a single DSP after optimizing our HEVC decoder. For HD formats, multi-DSP technology will be needed.(1)

关键词： HEVC DSP decoder complexity H.264

来源：评论

学校读者我要写书评

暂无评论

SVD-Assisted Joint Precoder and decoder Design for the Uplink of MU-MIMO Systems With Improper Modulation

引用

WIRELESS PERSONAL COMMUNICATIONS 2013年第3期73卷 1129-1142页

作者： Raja, M. Muthuchidambaranathan, P. Natl Inst Technol NIT Dept Elect & Commun Engn Tiruchirappalli Tamil Nadu India

This paper considers noniterative joint precoder and decoder design for uplink multi-user multiple-input, multiple-output systems, for both cases of perfect channel state information (CSI) and imperfect CSI at the transmitter and receiver. Instead of counting on complex iterative based algorithms, an efficient and noniterative SVD-based joint precoder and decoder pair design is employed. It also focusing on the scenario when an improper constellation such as binary phase shift-keying or -ary amplitude shift-keying (-ASK) is employed. The proposed are novel joint linear precoders and decoders design aims to minimize the total mean squared error of the symbol estimation. Simulations are conducted to provide a comparative evaluation of the proposed design over the previous designs on the bit-error-rate performance.

关键词： Multi-user multiple-input multiple-output (MU-MIMO) Uplink Singular value decomposition (SVD) Precoder decoder Channel state information (CSI) Total mean squared error (TMSE)

来源：评论

学校读者我要写书评

暂无评论

An Area-efficient Half-row Pipelined Layered LDPC decoder Architecture

引用

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 2017年第6期17卷 845-853页

作者： Ajaz, Sabooh Tram Thi Bao Nguyen Lee, Hanho Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea

This paper presents an area-efficient half-row pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the high-complexity bottleneck in fully parallel decoders. Synthesis results using TSMC 40 nm CMOS technology shows much better throughput at 10.84 Gbps and superior area efficiency, compared to previously reported LDPC decoders.

关键词： LDPC code half-row layered pipelined decoder

来源：评论

学校读者我要写书评

暂无评论

Embedded software optimization for AVS-P7 decoder real-time implementation on RISC core

引用

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2007年第3期53卷 1204-1210页

作者： Lei, Baiying Jin, Wenguang Hu, Jiwei Zhang, Xiaodong Zhejiang Univ Dept Informat & Elect Engn Hangzhou 310027 Peoples R China

AVS-P7 is the recent mobile video coding standard of China. Currently, ARM cores are widely used in mobile applications because of their low power consumption. In this paper, a scheme of the AVS-P7decoder real-time implementation on 32 bit MCU RISC processor ARM920T (S3C2440) is presented. The algorithm, redundancy, structure and memory optimization methods to implement AVS-P7 real-time are discussed in detail. The experiment results demonstrate the success of our optimization techniques and the real-time implementation. The ADS, MCPS, PSNR and simulation results show that the proposed AVS-P7 decoder can decode the OVGA image sequence in real-time with high image quality and has low complexity and less memory requirement. AVS conformance test result confirms the proposed AVS-P7 decoder full compliance with AVS. The proposed AVS-P7 decoder can be applied in many real-time applications like Mobile phone and IPTV in the third generation communication.

关键词： AVS-P7 decoder optimization RISC core

来源：评论

学校读者我要写书评

暂无评论

Design a Low-Power H.264/AVC Baseline decoder at All Abstraction Levels-A Showcase

引用

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第3期67卷 317-330页

作者： Xu, Ke Zhang, Min Choy, Chiu Sing Chinese Univ Hong Kong Dept Elect Engn Shatin Hong Kong Peoples R China

In this paper, we propose a low-power VLSI implementation of H. 264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency;hierarchical memory organization optimizes power-hungry memory accesses;hardware sharing reduces the total switching capacitance. At the circuit level, the knowledge about signal statistics is exploited to reduce number of transitions;data dependent signal-gating and clock-gating are introduced which are dynamic techniques for power reduction;multiplications are reduced and optimized, while complex dividers are totally eliminated. At the physical level, cell sizing and layout are optimized for power efficiency. The VLSI implementation shows that with UMC 0.18 mu m technology, the proposed design is able to decode realtime QCIF 30fps at 1.5 MHz. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4x4.4 mm(2) in a CQFP 208 package. The measured power consumption is 973 mu W @ 1.8 V and 293 mu W @ 1.0 V. The low-power and realtime features make our design ideal for portable or mobile applications.

关键词： decoder H.264/AVC Low-power Methodology

来源：评论

学校读者我要写书评

暂无评论

An anomaly detection method based on double encoder-decoder generative adversarial networks

引用

INDUSTRIAL ROBOT-THE INTERNATIONAL JOURNAL OF ROBOTICS RESEARCH AND APPLICATION 2021年第5期48卷 643-648页

作者： Liu, Hui Tang, Tinglong Luo, Jake Zhao, Meng Zheng, Baole Wu, Yirong China Three Gorges Univ Hubei Key Lab Intelligent Vis Based Monitoring Hy Yichang Peoples R China Univ Wisconsin Dept Hlth Informat & Adm Milwaukee WI 53201 USA Tianjin Univ Technol Tianjin Key Lab Intelligence Comp & Novel Softwar Tianjin Peoples R China China Three Gorges Univ Coll Comp & Informat Technol Yichang Peoples R China

Purpose - This study aims to address the challenge of training a detection model for the robot to detect the abnormal samples in the industrial environment, while abnormal patterns are very rare under this condition. Design/methodology/approach - The authors propose a new model with double encoder-decoder (DED) generative adversarial networks to detect anomalies when the model is trained without any abnormal patterns. The DED approach is used to map high-dimensional input images to a low-dimensional space, through which the latent variables are obtained. Minimizing the change in the latent variables during the training process helps the model learn the data distribution. Anomaly detection is achieved by calculating the distance between two low-dimensional vectors obtained from two encoders. Findings - The proposed method has better accuracy and Fl score when compared with traditional anomaly detection models. Originality/value - A new architecture with a DED pipeline is designed to capture the distribution of images in the training process so that anomalous samples are accurately identified. A new weight function is introduced to control the proportion of losses in the encoding reconstruction and adversarial phases to achieve better results. An anomaly detection model is proposed to achieve superior performance against prior state-of-the-art approaches.

关键词： Anomaly detection decoder Encoder Generative adversarial network

来源：评论

学校读者我要写书评

暂无评论

Low-Power Design for Unipolar ITO-Stabilized ZnO TFT RFID Code Generator Using Differential Logic decoder

引用

IEEE TRANSACTIONS ON ELECTRON DEVICES 2019年第11期66卷 4768-4773页

作者： Qin, Yuning Yeung, Fion S. Y. Wong, Man Kwok, Hoi Sing Li, Guoyuan Xu, Yuming Chen, Rongsheng Deng, Sunbin Zhong, Wei Wu, Zhaohui Li, Bin Li, Guijun South China Univ Technol Sch Elect & Informat Engn Guangzhou 510640 Guangdong Peoples R China Hong Kong Univ Sci & Technol Dept Elect & Comp Engn State Key Lab Adv Displays & Optoelect Tech Dept Elect & Comp Engn Hong Kong Peoples R China Shenzhen Univ Coll Elect Sci & Technol Shenzhen 518060 Peoples R China

This article proposes a low-power differential logic (DL) row/column decoder for radio frequency identification (RFID) code generators, which is used to optimize the power consumption of RFID at the circuit level. In addition, a pull-up control ring oscillator (PUC-RO) is also applied to further power optimization. For comparison, we fabricate three kinds of code generators with unipolar metal-oxide thin-film transistors (MO TFTs) using an indium tin oxide (ITO)-stabilized ZnO active channel layer. The power consumption of the code generator with a DL decoder is reduced by more than 20 % under the same supply voltage compared to the conventional pseudo-CMOS design. The power consumption of the code generator with a DL decoder and PUC-RO is reduced by more than 40 %. These results reveal a new perspective for power optimization of RFID tags based on TFTs technology.

关键词： Decoding Radiofrequency identification Power demand Inverters Logic gates Zinc oxide II-VI semiconductor materials decoder differential logic (DL) low power metal-oxide thin-film transistors (MO TFTs) radio frequency identification (RFID) code generator

来源：评论

学校读者我要写书评

暂无评论

decoder and Pass Transistor based Digitally Controlled Linear Delay Element 3

Decoder and Pass Transistor based Digitally Controlled Linea...

引用

3rd International Conference on Advances in Computing, Communications and Informatics (ICACCI)

作者： Sharma, Prachi Gupta, Anil Natl Inst Technol Sch VLSI Design & Embedded Syst Kurukshetra Haryana India

ISBN: (纸本)9781479930807

With advancement and scaling in Integrated circuit design, the accuracy of clock circuitry plays an increasingly important role. Timing precision is important to reduce the synchronization problem in digital circuits. The precise timing of pulse is also extremely important for designing asynchronous circuits. Delay element is the basic building block for asynchronous circuits. Many circuits of digitally controlled delay elements have been reported in literature. The reported circuits provide a delay which is a non linear function of digital inputs. Non linearity of delay in reported circuits affects the accuracy of time because of which they cannot be used in real world applications. This paper presents a novel circuit of decoder and pass transistor based delay element. The proposed circuit is designed for 3 bits and it provides a delay which is a linear function of digital inputs. The design is implemented in cadence using 180 nm CMOS technology.

关键词： delay element linearity decoder

来源：评论

学校读者我要写书评

暂无评论

decoder-Only Transformers: The Brains Behind Generative AI, Large Language Models and Large Multimodal Models

Decoder-Only Transformers: The Brains Behind Generative AI, ...

引用

2024 International Conference on Computing, Communication, Cybersecurity and AI

作者： Naik, Dishita Naik, Ishita Naik, Nitin Birmingham City Univ Birmingham W Midlands England King Edward VI Five Ways Sch Birmingham W Midlands England Aston Univ Sch Comp Sci & Digital Technol Birmingham W Midlands England

ISBN: (纸本)9783031744426;9783031744433

The rise of creative machines is attributed to generative AI which enabled machines to create new contents. Wherein the introduction of the advanced neural network architecture known as a transformer revolutionized the landscape of generative AI. A transformer transforms one sequence into another sequence, and is primarily used in natural language processing and computer vision tasks. Which determines the relationship between tokens or words in a sequence to understand the context, while processing these tokens or words simultaneously. Transformers were built to resolve various issues of its previous neural networks, such as a Recurrent Neural Network (RNN) and Long Short-Term Memory (LSTM);and are now the brains behind majority of generative AI models, for example Large Language Models (LLMs) and Large Multimodal Models (LMMs). This paper will explain about the transformer and its architectural components and working. Subsequently, it will illustrate the decoder-only transformer architecture and its components and working including the reason why this type of transformer architecture is used in most generative AI models such as LLMs and LMMs.

关键词： Transformer Attention Encoder decoder GPT Generative Pre-trained Transformer Unsupervised Pre-training SFT Supervised Fine-tuning LLMs Large Language Models LMMs Large Multimodal Models NLP Natural Language Processing GenAI Generative AI

来源：评论

学校读者我要写书评

暂无评论

Designing a 2-to-4 decoder on nanoscale based on quantum-dot cellular automata for energy dissipation improving

引用

OPTIK 2018年 158卷 477-489页

作者： Sherizadeh, Robab Navimipour, Nima Jafari Islamic Azad Univ Tabriz Branch Dept Comp Engn Tabriz Iran

Quantum dot Cellular Automata (QCA) as a new architecture at the nanoscale is developed as a feasible alternative for the existing Complementary Metal-Oxide-Semiconductor(CMOS) designs. The decoder in the QCA is a very important circuit to address the QCA-based random access memory arrays. It plays a key role in many circuit designs, such as Controlled Logic Block (CLB), Field Programmable Gate Array (FPGA), and memory circuits' designs. In this paper, a five-input majority gate is used in a modular design methodology to design a 2-to-4 decoder in QCA. The proposed 2-to-4 QCA-based decoder can be utilized to synthesize n-to-2(n) decoders as well. The functional correctness of the proposed circuit is evaluated using QCADesigner tool. Also, QCAPro simulator as a popular power estimator tool in QCA evaluates the power dissipation. The obtained results have shown the significant success in terms of clock speed (%57), wire-crossing (%33), cell number (%27), area (%26) and power dissipation than the existing designs. (C) 2017 Elsevier GmbH. All rights reserved.

关键词： Quantum dot cellular automata Power consumption decoder Nanoscale QCA

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：