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An Efficient Compatibility-Based Test Data Compression and Its decoder architecture

JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 2011年第6期27卷 787-796页

作者： Wan, Min-yong Ding, Yong Pan, Yun Yan, Xiao-lang Zhejiang Univ Inst VlSI Design Hangzhou 310027 Zhejiang Peoples R China

Test data compression is an effective methodology for reducing test data volume and testing time. A novel compatibility-based test data compression method is presented in this paper. With the high compression efficiency of extended frequency-directed run length coding algorithm, the proposed method groups the test vectors that have least incompatible bits and amalgamates them into a single vector by assigning 1 or 0 to unspecified bits and c to incompatible bits. Three runs of 1, 0 and c can be encoded simultaneously. In addition, the corresponding decoder architecture with low hardware overhead has been developed. To evaluate the effectiveness of the proposed approach, in experiments, it is applied to the International Symposium on Circuits and Systems' benchmark circuits. The experiments results show that the proposed algorithm gets a higher compression ratio than the conventional algorithms.

关键词： Test vector Compatibility Compression decoder architecture

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A Network-Efficient Nonbinary QC-LDPC decoder architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2012年第6期59卷 1359-1371页

作者： Zhang, Chuan Parhi, Keshab K. Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

Nonbinary low-density parity-check (LDPC) codes are of great interest due to their better performance cover binary ones when the code length is moderate. However, the cost of decoder implementation for these LDPC codes is still very high. In this paper, a low-complexity VLSI architecture for nonbinary LDPC decoders is presented. By exploiting the intrinsic shifting and symmetry properties of nonbinary quasi-cyclic LDPC (QC-LDPC) codes, significant reduction of memory size and routing complexity can be achieved. These unique features lead to two network-efficient decoder architectures for Class-I and Class-II nonbinary QC-LDPC codes, respectively. Comparison results with the state-of-the-art designs show that for the code example of the 64-ary (1260, 630) rate-0.5 Class-I code, the proposed scheme can save up to 70.6% hardware required by switch network, which demonstrates the efficiency of the proposed technique. The proposed design for the 32-ary (992, 496) rate-0.5 Class-II code can achieve a 93.8% switch network complexity reduction compared with conventional approaches. Furthermore, with the help of a generator for possible solution sequences, both forward and backward steps can be eliminated to offer processing convenience of check node unit (CNU) blocks. Results show the proposed 32-ary (992, 496) rate-0.5 Class-II decoder can achieve 4.47 Mb/s decoding throughput at a clock speed of 150 MHz.

关键词： decoder architecture geometry properties low-density parity-check (LDPC) codes nonbinary VLSI

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A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product decoder architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2018年第4期65卷 1420-1431页

作者： Condo, Carlo Giard, Pascal Leduc-Primeau, Francois Sarkis, Gabi Gross, Warren J. McGill Univ Dept Elect & Comp Engn Montreal PQ H3A 0G4 Canada Ecole Polytech Fed Lausanne Telecommun Circuits Lab CH-1015 Lausanne Switzerland IMT Atlantique F-29200 Brest France Qualcomm Res Syst Grp San Diego CA 92121 USA

Powerful forward error correction (FEC) schemes are used in optical communications to achieve bit-error rates (BERs) below 10-15. These FECs follow one of two approaches: the concatenation of simpler hard-decision codes or the usage of inherently powerful soft-decision codes. The first approach yields lower net coding gains (NCGs), but can usually work at higher code rates and have lower complexity decoders. In this paper, we propose a novel FEC scheme based on a product code and a post-processing technique. It can achieve an NCG of 9.52 dB at a BER of 10(-15) and 9.96 dB at a BER of 10(-18), an error-correction performance that sits between that of current hard-decision and soft-decision FECs. A decoder architecture is designed, tested on field programmable gate array and synthesized in 65-nm CMOS technology: its 162 b/cycle worst-case information throughput can reach 100 Gb/s at the achieved frequency of 616 MHz. Its complexity is shown to be lower than that of hard-decision decoders in literature, and an order of magnitude lower than the estimated complexity of soft-decision decoders.

关键词： Channel coding product codes decoder architecture VLSI

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Efficient Configurable decoder architecture for Nonbinary Quasi-Cyclic LDPC Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2012年第1期59卷 188-197页

作者： Chen, Xiaoheng Lin, Shu Akella, Venkatesh Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

Nonbinary LDPC codes are effective in combating burst errors. This paper presents an efficient architecture for implementing nonbinary LDPC decoders. The Galois field power representation is used to organize the a priori, a posteriori, and extrinsic messages involved in decoding. The power representation in conjunction with the barrel shifter and multithreaded pipelining yields an efficient implementation. The proposed decoder is configurable, in the sense that a single decoder can be used to decode any code of a given field size. The decoder supports both regular and irregular nonbinary QC-LDPC codes. Using a practical metric of throughput per unit area, the proposed implementation outperforms the best implementations published in research literature to date.

关键词： Configurable decoder architecture low-density parity-check (LDPC) codes min-max nonbinary VLSI design

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A Fixed Latency ORBGRAND decoder architecture With LUT-Aided Error-Pattern Scheduling

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2022年第5期69卷 2203-2211页

作者： Condo, Carlo Infinera Corp Ottawa ON K2K 2X3 Canada

Guessing Random Additive Noise Decoding (GRAND) is a universal decoding algorithm that has been recently proposed as a practical way to perform maximum likelihood decoding. It generates a sequence of possible error patterns and applies them to the received vector, checking if the result is a valid codeword. Ordered reliability bits GRAND (ORBGRAND) improves on GRAND by considering soft information received from the channel. Both GRAND and ORBGRAND have been implemented in hardware, focusing on average performance, sacrificing worst case throughput and latency. In this work, an improved pattern schedule for ORBGRAND is proposed. It provides >0.5 dB gain over the standard schedule at a block error rate <= 10(-5), and outperforms more complex GRAND flavors with a fraction of the complexity. The proposed schedule is used within a novel code-agnositic decoder architecture: the decoder guarantees fixed high throughput and low latency, making it attractive for latency-constrained applications. It outperforms the worst-case performance of decoders by orders of magnitude, and outperforms many best-case figures. Decoding a code of length 128, it achieves a throughput of 79.21 Gb/s with 58.49 ns latency, yielding better energy efficiency and comparable area efficiency with respect to the state of the art.

关键词： Guessing random additive noise decoding (GRAND) maximum likelihood (ML) ordered reliability bits GRAND (ORBGRAND) decoder architecture VLSI low latency high throughput

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An Efficient NB-LDPC decoder architecture for Space Telecommand Links

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2021年第4期68卷 1213-1217页

作者： Alvarez, Angel Fernandez, Victor Matuz, Balazs Univ Cantabria Microelect Engn Grp Santander 39005 Spain German Aerosp Ctr DLR Inst Commun & Nav D-82234 Webling Germany

In the framework of error correction in space telecommand (TC) links, the Consultative Committee for Space Data Systems (CCSDS) currently recommends short block-length BCH and binary low-density parity-check (LDPC) codes. Other alternatives have been discarded due to their high decoding complexity, such as non-binary LDPC (NB-LDPC) codes. NB-LDPC codes perform better than their binary counterparts over AWGN and jamming channels, being great candidates for space communications. We show the feasibility of NB-LDPC coding for space TC applications by proposing a highly efficient decoding architecture. The proposed decoder is implemented for a (128,64) NB-LDPC code over GF(16) and the design is particularized for a space-certified Virtex-5QV FPGA. The results prove that NB-LDPC coding is an alternative that outperforms the standardized binary LDPC, with a coding gain of 0.7 dB at a reasonable implementation cost. Given that the maximum rate for TC recommended by the CCSDS is 2 Mbps, the proposed architecture achieves a throughput of 2.03 Mbps using only 9615 LUTs and 5637 FFs (no dedicated memories are used). In addition, this architecture is suitable for any regular (2,4) NB-LDPC (128,64) code over GF(16) independently of the H matrix, allowing flexibility in the choice of the code. This brief places NB-LDPC codes as the excellent candidates for future versions of the telecommand uplink standard.

关键词： Decoding Computer architecture Encoding Complexity theory Iterative decoding Throughput VLSI design FPGA non-binary LDPC codes decoder architecture space communications

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Hardware-Oriented Turbo-Product Codes decoder architecture 9

Hardware-Oriented Turbo-Product Codes Decoder Architecture

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9th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems - Technology and Applications (IDAACS)

作者： Krainyk, Yaroslav Perov, Vladyslav Musiyenko, Maksym Davydenko, Yevhen Petro Mohyla Black Sea Natl Univ Dept Comp Engn Mykolaiv Ukraine

ISBN: (纸本)9781538606971

Model of Turbo-Product Codes decoder architecture and method for construction of Turbo-Product Codes decoder are proposed in the paper. The model describes decoder functioning taking into account limitations of hardware platform and proposes re-use of components in the decoding process. The method provides set of steps for decoder implementation. Field-Programmable Gate Arrays circuits are selected as hardware platform. Implemented decoder demonstrates high throughput and can decode codes that consist of Hamming codes with different codeword length that can be configured "on-the-fly".

关键词： TPC-decoder hardware utilization decoder architecture memory blocks decoder implementation

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An Exp-Golomb encoder and decoder architecture for JVT/AVS 5

An Exp-Golomb encoder and decoder architecture for JVT/AVS

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5th International Conference on ASIC

作者： Wu, D Gao, W Hu, MZ Ji, ZZ Harbin Inst Technol Dept Comp Sci & Engn Harbin Peoples R China

ISBN: (纸本)078037889X

In recent years, the Exp-Golomb coding, a form of variable length coding (VLC), has gained greater attention due to its important uses in the emerging JVT (also called H.264 in ITU, and AVC in MPEG-4) and AVS (self-developed Chinese audio video standard). In this paper, the Exp-Golomb encoder and decoder architectures for JVT and AVS are proposed for the first time. To solve the key problem associated with determining the code length in the Exp-Golomb encoding and decoding, we use an approach called 'the first 1 detect method' that can greatly simplify the architectures The areas of the encoder and decoder proposed ire 2048 and 3210 gates respectively. which pretty small. The critical path delays in both architectures are less than 6ns. Therefore. these designs can meet the requirement of high speed for the encoding and decoding in real time.

关键词： logic circuits logic design variable length codes Exp-Golomb encoder decoder architecture JVT-AVS Exp-Golomb coding variable length coding H.264 ITU MPEG-4 AVS Chinese audio video standard code length first 1 detect method critical path delays

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Low-Complexity Entirely-Overlapped Parallel decoder architecture for Quasi-Cyclic LDPC Codes

Low-Complexity Entirely-Overlapped Parallel Decoder Architec...

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11th International Conference on Advanced Communication Technology

作者： Lu, Weizhi Ma, Piming Shandong Univ Sch Informat Sci & Engn Jinan 250100 Peoples R China

ISBN: (纸本)9788955191387

In this paper, we propose a low-complexity entirely-overlapped partially-parallel decoder architecture for quasi-cyclic low-density parity-check (QC-LDPC) codes. For a (c, t)-regular QC-LDPC decoder, this decoder can achieve approximate 100% hardware utilization efficiency (HUE) and entirely overlapped decoding by using only one check node process unit group (CNUG) to process c groups of check node messages sequentially. Compared with traditional partially-parallel decoder, the quantities of check node process unit (CNU), barrel shifters and counters can be decreased prominently. Moreover, it is flexible in code rate and code length.

关键词： QC-LDPC codes HUE entirely-overlapped partially-parallel decoder architecture

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A Fast Successive Cancellation List decoder for Polar Codes With an Early Stopping Criterion

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2018年第18期66卷 4971-4979页

作者： Kim, Daesung Park, In-Cheol Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon 305701 South Korea

The successive cancellation list (SCL) decoding is the most powerful decoding algorithm for polar codes. However, the long latency makes it unsuitable for practical applications, and thus many algorithms have been presented to resolve the problem. While most of the previous algorithms have reduced the latency by pruning unnecessary operations in the middle of the process, this paper proposes an early stopping criterion. The proposed method can determine the minimum metric path without having to traverse the tree to the end if a special condition is satisfied at a certain point. The remaining bits located after the stopped bit position are decoded directly from the soft information. The simulation results show that the criterion reduces the decoding latency effectively for various code rates and list sizes without any performance loss. We also propose a hardware architecture that is efficient in realizing the proposed method. Compared to previous SCL decoding algorithms, the proposed decoder achieves 16% higher throughput and 12% improved area efficiency at an SNR of 5.0 dB when the list size is 4.

关键词： Polar codes SCL decoding early stopping decoder architecture

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