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Reed-Solomon decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems

CIRCUITS SYSTEMS AND SIGNAL PROCESSING 2019年第4期38卷 1793-1810页

作者： Perrone, Gabriele Valls, Javier Torres, Vicente Garcia-Herrero, Francisco ABB SACE Vittuone Italy Univ Politecn Valencia Inst Telecomunicac & Aplicac Multimedia ITEAM Valencia 46022 Spain European Univ Miguel Cervantes Valladolid Spain Univ Antonio Nebrija ARIES Res Ctr Madrid 28040 Spain

Several 100Gbps Ethernet standards for backplane, copper cables and fiber optic that include forward error correction based on Reed-Solomon (RS) codes have been recently approved, being an important issue not only to achieve high data rates but also to keep a low latency. This paper presents two low-latency and high-throughput RS decoders suitable for those standards. We propose the use of a modified Enhanced Parallel iBM Algorithm as the key equation solver (KES) stage and a novel architecture for the error evaluation block, which is suited for this KES. Implementation results are given for the RS(528,514) and RS(544,514) codes over GF(210) that reach 100Gbps when implemented in a 90nm CMOS process.

关键词： Reed-Solomon decoder architecture High throughput Low latency ePIBMA

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A 2.0 Gb/s Throughput decoder for QC-LDPC Convolutional Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2013年第7期60卷 1857-1869页

作者： Sham, Chiu-Wing Chen, Xu Lau, Francis C. M. Zhao, Yue Tam, Wai M. Hong Kong Polytech Univ Dept Elect & Informat Engn Hong Kong Hong Kong Peoples R China

This paper proposes a decoder architecture for low-density parity-check convolutional code (LDPCCC). Specifically, the LDPCCC is derived from a quasi-cyclic (QC) LDPC block code. By making use of the quasi-cyclic structure, the proposed LDPCCC decoder adopts a dynamic message storage in the memory and uses a simple address controller. The decoder efficiently combines the memories in the pipelining processors into a large memory block so as to take advantage of the data-width of the embedded memory in a modern field-programmable gate array (FPGA). A rate-5/6 QC-LDPCCC has been implemented on an Altera Stratix FPGA. It achieves up to 2.0 Gb/s throughput with a clock frequency of 100 MHz. Moreover, the decoder displays an excellent error performance of lower than 10(-13) at a bit-energy-to-noise power-spectral-density ratio(E-b/N-0) of 3.55 dB.

关键词： decoder architecture FPGA implementation LDPC convolutional code QC-LDPC convolutional code

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Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension

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IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS 2023年第5期59卷 5835-5846页

作者： Kuo, Yao-Ming Flanagan, Mark F. Garcia-Herrero, Francisco Ruano, Oscar Antonio Maestro, Juan Monolith Power Syst Barcelona 08029 Spain Univ Coll Dublin Sch Elect & Elect Engn Dublin 4 Ireland Univ Complutense Madrid Dept Comp Architecture & Automat Madrid 28040 Spain

The Consultative Committee for Space Data Systems (CCSDS) recommends the use of short-block length Bose-Chaudhuri-Hocquenghem and binary low-density parity-check codes. Despite the high error-correction capacity of nonbinary low-density parity-check (NB-LDPC) codes, they have not yet been considered due to their high decoding complexity. In this article, the feasibility of NB-LDPC coding for space telecommand link applications using an RISC-V soft-core processor plus a vector coprocessor is demonstrated. The purpose of this article is to avoid the need for a dedicated decoder hardware, and thus, the customized general-purpose processor that performs decoding can be reconfigured to perform other important onboard tasks. In this way, the logic utilization and power consumption can be reduced since more functionalities can be assumed by the onboard processor. The method of acceleration of an NB-LDPC decoder over GF(16) using the RISC-V vector extension is demonstrated, and a throughput of 8.48 kb/s is achieved for the forward-backward implementation of the min-max decoding algorithm, which is compatible with the low-rate and mid-rate telecommand systems recommended by the CCSDS.

关键词： Decoding Computer architecture Program processors Field programmable gate arrays Symbols Standards Reliability decoder architecture field-programmable gate array (FPGA) nonbinary low-density parity-check (NB-LDPC) codes RISC-V soft-core processors space communications

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Design of an Efficient Maximum Likelihood Soft decoder for Systematic Short Block Codes

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2012年第7期60卷 3914-3919页

作者： Adde, Patrick Toro, Daniel Gomez Jego, Christophe Telecom Bretagne Inst Telecom CNRS Lab STICC UMR 3192 F-29238 Brest France Univ Bordeaux CNRS IMS IPB Enseirb Matmeca UMR 5218 F-33405 Talence France

Maximum likelihood soft-decision decoding of linear block codes is addressed in this correspondence. A novel algorithm based on Chase-2 algorithm for the decoding of systematic binary block codes is detailed. A double re-encoding technique in place of the classical algebraic decoding for the computation of the candidate codeword list is the major innovation of the proposed algorithm. This approach has been successfully applied to systematic block codes that have a code rate equal to 1/2 and a parity check matrix composed of an invertible submatrix for the redundancy part. Simulation results show performance close to the optimum maximum likelihood decoding for an excellent tradeoff between BER performance and computational complexity. Then, the challenging issue of designing a decoder for a specific family of short binary block codes, called Cortex codes is also described. Three soft decoders for Cortex codes with lengths equal to 32, 64, and 128 and a code rate equal to 1/2 have been designed. Then, all the decoders were successively implemented onto an field-programmable gate array (FPGA) device. To our knowledge, they are the first efficient digital implementations of Cortex codes.

关键词： Computational complexity decoder architecture re-encoding soft decoding systematic short bloc codes

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A Reconfigurable TDMP decoder for Raptor Codes

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2012年第3期69卷 293-304页

作者： Zeineddine, Hady Mansour, Mohammad M. Amer Univ Beirut Beirut Lebanon

A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform ( LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: ( 1) applying systematic permutations on the source matrix of the Raptor code, ( 2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of rowsplitting scenarios, and ( 3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT-and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/ s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm2.

关键词： Raptor codes Reconfigurable decoder Error-correcting code decoder architecture

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An 847-955 Mb/s 342-397 mW Dual-Path Fully-Overlapped QC-LDPC decoder for WiMAX System in 0.13 μm CMOS

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2011年第6期46卷 1416-1432页

作者： Xiang, Bo Bao, Dan Huang, Shuangqu Zeng, Xiaoyang Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

This paper presents a partially-parallel dual-path fully-overlapped QC-LDPC decoder for the WiMAX system. By adopting five techniques including symmetrical six-stage pipelining, block column and row interleaving, nonzero sub-matrix reordering, sum memory quad-partition and read-write bypass, the decoder continuously scans nonzero sub-matrices two by two in the block row-wise order without any memory access conflict. Two phases are fully overlapped with each other, and the check node updating phase always takes the latest sums from the previous variable node updating phase. The sum memory stores not only the posterior sums but also the prior messages, which saves 11,520 memory bits. It only takes 48-54 clock cycles for the decoder to finish one iteration. The read-write accesses to sum memories are reduced by 24.3%-48.8%. Fabricated in the SMIC 0.13 mu m CMOS process, the decoder occupies 4.84 mm(2) with core area of 3.03 mm(2), attains 847-955 Mb/s at 214 MHz and 10 iterations, and consumes 342-397 mW at 1.2 V with power efficiency of 39-46 pJ per bit per iteration.

关键词： Block column and row interleaving decoder architecture dual-path fully-overlapped nonzero sub-matrix reordering QC-LDPC codes read-write bypass symmetrical six-stage pipelining

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High-Throughput Efficient Non-Binary LDPC decoder Based on the Simplified Min-Sum Algorithm

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2012年第11期59卷 2784-2794页

作者： Chen, Xiaoheng Wang, Chung-Li SanDisk Corp Milpitas CA 95035 USA LSI Corp Milpitas CA 95035 USA

Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64 X area efficiency improvement even compared with the most state-of-the-art design.

关键词： decoder architecture error control coding low-density parity-check (LDPC) codes non-binary VLSI design

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Soft input decoder for high-rate generalised concatenated codes

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IET CIRCUITS DEVICES & SYSTEMS 2018年第4期12卷 432-438页

作者： Spinner, Jens Rohweder, Daniel Freudenberger, Juergen Univ Appl Sci HTWG Konstanz ISD Constance Germany

Generalised concatenated (GC) codes are well suited for error correction in flash memories for high-reliability data storage. The GC codes are constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. The extended BCH codes enable high-rate GC codes and low-complexity soft input decoding. This work proposes a decoder architecture for high-rate GC codes. For such codes, outer error and erasure decoding are mandatory. A pipelined decoder architecture is proposed that achieves a high data throughput with hard input decoding. In addition, a low-complexity soft input decoder is proposed. This soft decoding approach combines a bit-flipping strategy with algebraic decoding. The decoder components for the hard input decoding can be utilised which reduces the overhead for the soft input decoding. Nevertheless, the soft input decoding achieves a significant coding gain compared with hard input decoding.

关键词： concatenated codes error correction codes flash memories integrated circuit reliability binary codes BCH codes Reed-Solomon codes decoding computational complexity soft input decoder high-rate generalised concatenated codes error correction flash memories high-reliability data storage inner extended binary Bose-Chaudhuri-Hocquenghem codes outer Reed-Solomon codes extended BCH codes high-rate GC codes low-complexity soft input decoding decoder architecture outer error erasure decoding pipelined decoder architecture hard input decoding low-complexity soft input decoder soft decoding approach bit-flipping strategy algebraic decoding coding gain

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VLSI Implementation of a Non-Binary decoder Based on the Analog Digital Belief Propagation

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IEEE TRANSACTIONS ON SIGNAL PROCESSING 2014年第15期62卷 3965-3975页

作者： Awais, Muhammad Masera, Guido Martina, Maurizio Montorsi, Guido Comsats Inst Informat Technol Dept Elect Engn Wah Cantt 47040 Pakistan Politecn Torino Dept Elect & Telecommun I-10129 Turin Italy

This work presents the VLSI hardware implementation of a novel Belief Propagation (BP) algorithm introduced in [G. Montorsi, "Analog digital belief propagation," IEEE Commun. Lett., vol. 16, no. 7, pp. 1106-1109, 2012] and named as Analog Digital Belief Propagation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by tracking their parameters. In particular, ADBP can deal with system variables that are discrete and/or wrapped. A variant of ADBP can then be applied for the iterative decoding of a particular class of non binary codes and yields decoders with complexity independent of alphabet size, thus allowing to construct efficient decoders for digital transmission systems with unbounded spectral efficiency. In this work, we propose some simplifications to the updating rules for ADBP algorithm that are suitable for hardware implementation. In addition, we analyze the effect of finite precision on the decoding performance of the algorithm. A careful selection of quantization scheme for input, output and intermediate variables allows us to construct a complete ADBP decoding architecture that performs close to the double precision implementation and shows a promising complexity for large values of. Finally, synthesis results of the main processing elements of ADBP are reported for 45 nm standard cell ASIC technology.

关键词： Analog Digital Belief Propagation APP estimation belief propagation decoder architecture iterative decoding non binary LDPC VLSI decoder

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Efficient decoder Design for Nonbinary Quasicyclic LDPC Codes

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2010年第5期57卷 1071-1082页

作者： Lin, Jun Sha, Jin Wang, Zhongfeng Li, Li Nanjing Univ Inst VLSI Design Dept Phys Jiangsu Prov Key Lab Adv Photon & Elect Mat Nanjing 210093 Peoples R China Broadcom Corp Irvine CA 92617 USA

This paper addresses decoder design for nonbinary quasicyclic low-density parity-check (QC-LDPC) codes. First, a novel decoding algorithm is proposed to eliminate the multiplications over Galois field for check node processing. Then, a partially parallel architecture for check node processing units and an optimized architecture for variable node processing units are developed based on the new decoding algorithm. Thereafter, an efficient decoder structure dedicated to a promising class of high-performance nonbinary QC-LDPC codes is presented for the first time. Moreover, an ASIC implementation for a (620, 310) nonbinary QC-LDPC code decoder over GF(32) is designed to demonstrate the efficiency of the presented techniques.

关键词： decoder architecture extended min-sum (EMS) fast Fourier transform (FFT) belief propagation (BP) Min-Max decoding nonbinary quasicyclic low-density parity-check (QC-LDPC) codes very large scale integration (VLSI)

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