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Test data compression using hierarchical block merging technique

IET COMPUTERS AND DIGITAL TECHNIQUES 2018年第4期12卷 176-185页

作者： Vohra, Harpreet Singh, Amardeep Thapar Inst Engingeering & Technol Elect & Commun Engn Dept Patiala Punjab India Punjabi Univ Comp Sci & Engn Dept Patiala Punjab India

Manufacturing of semiconductor devices at the sub-micron level has led to the introduction of huge number of faults. To ensure the quality of integrated circuits (ICs), enormous amount of test data is needed which, in turn, increases the overall test cost of the ICs. This study presents a hierarchical block-merging-based technique (HBMT) for test data compression, which appropriately encodes the test pattern blocks of fixed sizes at inter- and intra-block levels using lesser number of bits. The proposed technique works in four steps: segmentation of the entire length of test data into equal length blocks;categorisation of test blocks as compatible blocks and unique blocks;merging of compatible blocks to form representative pattern block, which is further merged at sub-block level;and compression of the non-compatible (unique) blocks using different encoding cases. Experimental results performed on various international symposium for circuits and systems (ISCAS)' 89 benchmark circuits demonstrate the effectiveness of the proposed test data compression technique. It is found that application of HBMT can improve the compression efficiency by an average of 73% along with a reduction in the test application time. This study also presents the decoder architecture.

关键词： data compression merging test data compression hierarchical block merging technique semiconductor device manufacturing integrated circuit quality HBMT test data segmentation test blocks categorisation ISCAS 89 benchmark circuits decoder architecture

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Gallager codes for CDMA applications - Part II: Implementations, complexity, and system capacity

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IEEE TRANSACTIONS ON COMMUNICATIONS 2000年第11期48卷 1818-1828页

作者： Sorokine, V Kschischang, FR Pasupathy, S Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

We focus our attention on Gallager codes with parameters compatible with the IS-95 cellular radio standard. We discuss low complexity software and hardware implementations of an iterative decoder for {N, -, 3} Gallager codes. We estimate that by using Gallager codes, a factor of five improvement in the code-division multiple-access system capacity relative to an uncoded system can be achieved, equivalent to a factor of two improvement relative to state-of-the art orthogonal convolutional codes. Simulation results demonstrate the good performance of short-frame Gallager codes in the additive white Gaussian noise and certain fading channels.

关键词： complexity theory decoder architecture information rates low-density parity-check codes

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Review on 5G NR LDPC Code: Recommendations for DTTB System

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IEEE ACCESS 2021年 9卷 155413-155424页

作者： Li, Fengshuang Zhang, Chao Peng, Kewu Krylov, Aleksei E. Katyushnyj, Aleksandr A. Rashich, Andrey, V Tkachenko, Dmitry A. Makarov, Sergey B. Song, Jian Tsinghua Univ Dept Elect Engn Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China Peter Great St Petersburg Polytech Univ Higher Sch Appl Phys & Space Technol St Petersburg 195251 Russia

The freeze of the 5th generation new radio (5G NR) Release 16 indicates that 5G development has stepped into a new stage. The application of a dedicated low-density parity-check (LDPC) code for channel coding is an important technical advance that distinguishes 5G NR from the 4th generation (4G) long-term evolution (LTE) and LIE-advanced. Although LDPC codes have been used in many different systems, the newly developed LDPC code in 5G NR integrates many cutting-edge technologies to provide better performance and attractive features. Thus, it can be a good reference for channel coding in other evolving systems headed by digital terrestrial television broadcasting (DTTB). In emerging applications, the DTTB system needs to carry information with higher density, while meeting the high requirements for real-time, coverage, and bit error rate of broadcasting. To provide a reference for DTTB channel coding that improves its performance and supports new services, a review of 5G NR LDPC code implementation is carried out from three aspects: code analysis and design, decoding algorithm, and decoder architecture. We thoroughly evaluate each solution and highlight some candidates for existing implementations or directions for further development of the DTTB system.

关键词： Low-density parity-check (LDPC) code digital terrestrial television broadcasting (DTTB) 5th generation new radio (5G NR) code design decoding algorithm decoder architecture

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Decoding Algorithm and architecture for BCH Codes under the Lee Metric

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IEEE TRANSACTIONS ON COMMUNICATIONS 2008年第12期56卷 2050-2059页

作者： Wu, Yingquan Hadjicostis, Christoforos N. Univ Illinois Coordinated Sci Lab Urbana IL 61801 USA Univ Illinois Dept Elect & Comp Engn Urbana IL 61801 USA Univ Cyprus Dept Elect & Comp Engn Nicosia Cyprus

The Lee metric measures the circular distance between two elements in a cyclic group and is particularly appropriate as a measure of distance for data transmission under phase-shift-keying modulation over a white noise channel. In this paper, using newly derived properties on Newton's identities, we initially investigate the Lee distance properties of a class of BCH codes and show that (for an appropriate range of parameters) their minimum Lee distance is at least twice their designed Hamming distance. We then make use of properties of these codes to devise an efficient algebraic decoding algorithm that successfully decodes within the above lower bound of the Lee error-correction capability. Finally, we propose an attractive design for the corresponding VLSI architecture that is only mildly more complex than popular decoder architectures under the Hamming metric;since the proposed architecture can also be used for decoding under the Hamming metric without extra hardware, one can use the proposed architecture to decode under both distance metrics (Lee and Hamming).

关键词： BCH codes Lee distance algebraic decoder decoder architecture

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Online log-likelihood ratio scaling for robust turbo decoding

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IET COMMUNICATIONS 2014年第2期8卷 217-226页

作者： El-Khamy, Mostafa Wu, Jinhong Lee, Jungwon Kang, Inyup Samsung Res Amer Mobile Solut Lab San Diego CA 92121 USA

Optimal iterative log-MAP decoding of turbo codes requires accurate knowledge of the operating signal-to-noise ratio (SNR). However, the SNR information, available at practical decoders for bit-interleaved coded modulation systems, such as the third generation partnership project high-speed packet access and long-term evolution wireless cellular systems, may be inaccurate. In this study, two decoder architectures for improved turbo decoding in the presence of SNR mismatch are proposed. The SNR-mismatch aware turbo decoder selects the decoder which is estimated to have the best performance at the current mismatch, according to the test criterion. The SNR-mismatch compensated turbo decoder provides a more accurate estimation of the noise variance and concurrently scales the channel and the decoder log-likelihood ratios (LLRs) to continue decoding. Two different methods are proposed to find the optimal scaling factors online, one on the symbol level and the other on the bit level. This study shows that online LLR scaling, without prior knowledge about the noise mismatch statistics, can result in near-optimal turbo decoding regardless of the initial SNR mismatch.

关键词： iterative decoding maximum likelihood decoding modulation coding radiocommunication turbo codes online log likelihood ratio scaling robust turbo decoding optimal iterative log-MAP decoding turbo codes decoder log-likelihood ratio signal-to-noise ratio mismatch decoder architecture bit-interleaved coded modulation systems

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Systematic construction, verification and implementation methodology for LDPC codes

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EURASIP JOURNAL ON WIRELESS COMMUNICATIONS AND NETWORKING 2012年第1期2012卷 1-13页

作者： Yu, Hui Cui, Jing Wang, Yixiang Yang, Yibin Shanghai Jiao Tong Univ Dept Elect Engn Shanghai 200030 Peoples R China

In this article, a novel and systematic Low-density parity-check (LDPC) code construction, verification and implementation methodology is proposed. The methodology is composed by the simulated annealing based LDPC code constructor, the GPU based high-speed code selector, the ant colony optimization based pipeline scheduler and the FPGA-based hardware implementer. Compared to the traditional ways, this methodology enables us to construct both decoding-performance-aware and hardware-efficiency-aware LDPC codes in a short time. Simulation results show that the generated codes have much less cycles (length 6 cycles eliminated) and memory conflicts (75% reduction on idle clocks), while having no BER performance loss compared to WiMAX codes. Additionally, the simulation speeds up by 490 times under float precision against CPU and a net throughput 24.5 Mbps is achieved. Finally, a net throughput 1.2 Gbps (bit-throughput 2.4 Gbps) multi-mode LDPC decoder is implemented on FPGA, with completely on-the-fly configurations and less than 0.2 dB BER performance loss.

关键词： low-density parity-check codes simulated annealing ant colony optimization graphic processing unit decoder architecture

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A Soft Input Decoding Algorithm for Generalized Concatenated Codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2016年第9期64卷 3585-3595页

作者： Spinner, Jens Freudenberger, Juergen Shavgulidze, Sergo Univ Appl Sci HTWG Konstanz Inst Syst Dynam D-78462 Constance Germany Georgian Tech Univ Fac Power Engn & Telecommun GE-0175 Tbilisi Georgia

This paper proposes a soft input decoding algorithm and a decoder architecture for generalized concatenated (GC) codes. The GC codes are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon codes. In order to enable soft input decoding for the inner BCH block codes, a sequential stack decoding algorithm is used. Ordinary stack decoding of binary block codes requires the complete trellis of the code. In this paper, a representation of the block codes based on the trellises of supercodes is proposed in order to reduce the memory requirements for the representation of the BCH codes. This enables an efficient hardware implementation. The results for the decoding performance of the overall GC code are presented. Furthermore, a hardware architecture of the GC decoder is proposed. The proposed decoder is well suited for applications that require very low residual error rates.

关键词： Generalized concatenated codes Bose-Chaudhuri-Hocquenghem codes Reed-Solomon code codes decoder architecture soft input decoding flash memory

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Reconfigurable architecture and Automated Design Flow for Rapid FPGA-based LDPC Code Emulation 12

Reconfigurable Architecture and Automated Design Flow for Ra...

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20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

作者： Li, Haoran Park, Youn Sung Zhang, Zhengya Univ Michigan Dept Elect Engn & Comp Sci Ann Arbor MI 48109 USA

ISBN: (纸本)9781450311557

Multitude of design freedoms of LDPC codes and practical decoders require fast simulations. FPGA emulation is attractive but inaccessible due to its design complexity. We propose a library and script based approach to automate the construction of FPGA emulations. Code parameters and design parameters are programmed either during run time or by script in design time. We demonstrate the architecture and design flow using the LDPC codes for the latest wireless communication standards: each emulation model was auto-constructed within one minute and the peak emulation throughput reached 3.8 Gb/s on a BEE3 platform.

关键词： LDPC decoder emulation decoder architecture

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A Single Parity Check Forward Error Correction Method for High Speed I/O

A Single Parity Check Forward Error Correction Method for Hi...

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IEEE Global Conference on Signal and Information Processing (GlobalSIP)

作者： Kiran, Shiva Hoyos, Sebastian Palermo, Samuel Texas A&M Univ Dept Elect & Comp Engn College Stn TX 77843 USA

ISBN: (纸本)9781479970889

Some proposed high speed wireline communications make use of an ADC front end to allow a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the channel. High precision ADCs are expensive in terms of power. The FFE block performs multiplication and addition operations at high speed and further increases the power consumption. This paper proposes a simple forward error correction method by which the ADC resolution and the equalizer complexity can be reduced. A single parity check code implemented together with a threshold detector can provide single error correction capability. With this error correction capability, the number of taps required in the FFE block is shown to be reduced to 3 taps from 6 taps for a channel with 15dB insertion loss at 5GHz frequency with the data rate being 20Gb/s. The effective number of bits (ENOB) required from the ADC is also shown to reduce to about 3.5 bits from 6 bits. The high rate of the code and the very simple decoder architecture make this error correction mechanism well suited for the wireline application.

关键词： codecs equalisers forward error correction parity check codes ADC resolution ENOB bit rate 20 Gbit/s decoder architecture effective number of bits equalizer complexity forward error correction method frequency 5 GHz high speed I/O insertion loss loss 15 dB single error correction capability single parity check code threshold detector Bit error rate Decoding Encoding Equalizers Forward error correction Parity check codes Receivers

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Implementation of message-passing algorithms for the acquisition of spreading codes

Implementation of message-passing algorithms for the acquisi...

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33rd IEEE International Conference on Acoustics, Speech and Signal Processing

作者： Rovini, Massimo Principe, Fabio Fanucci, Luca Luise, Marco Univ Pisa Dept Informat Engn I-56122 Pisa Italy

ISBN: (纸本)9781424414833

A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative Message Passing (iMP) to be run on loopy graph. This technique approximates the maximum-likelihood (ML) estimator, providing a sub-optimal algorithm that searches all possible code phases in parallel, at low complexity and fast acquisition time. This work is addressed to the design of the architecture of an iMP detector, following the implementation methodologies typical of standard low-density parity-check (LDPC) decoders, and demonstrates its benefits in terms of acquisition time and complexity, compared with standard techniques.

关键词： message passing low-density parity-check codes code division multiple access decoder architecture system design

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