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An LDPC decoder chip based on self-routing network for IEEE 802.16e applications

IEEE JOURNAL OF SOLID-STATE CIRCUITS 2008年第3期43卷 684-694页

作者： Liu, Chih-Hao Yen, Shau-Wei Chen, Chih-Lung Chang, Hsie-Chia Lee, Chen-Yi Hsu, Yar-Sun Jou, Shyh-Jye Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

An LDPC decoder chip fully compliant to IEEE 802.16e applications is presented. Since the parity check matrix can be decomposed into sub-matrices which are either a zero-matrix or a cyclic shifted matrix, a phase-overlapping message passing scheme is applied to update messages immediately, leading to enhance decoding throughput. With only one shifter-based permutation structure, a self-routing switch network is proposed to merge 19 different sub-matrix sizes as defined in IEEE 802.16e and enable parallel message to be routed without congestion. Fabricated in the 90 nm 1P9M CMOS process, this chip achieves 105 Mb/s at 20 iterations while decoding the rate-5/6 2304-bit code at 150 MHz operation frequency. To meet the maximum data rate in IEEE 802.16e, this chip operates at 109 MHz frequency and dissipates 186 mW at 1.0 V supply.

关键词： decoder architectures IEEE 802.16 iterative decoders LDPC codes phase-overlapping self-routing WiMax

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A Novel Energy-Efficient MIMO-OFDM decoder Architecture with Error Detection

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IETE JOURNAL OF RESEARCH 2023年第4期69卷 1974-1984页

作者： Preethi, D. Valarmathi, R. S. Bannari Amman Inst Technol Dept Elect & Commun Engn Erode Tamil Nadu India

Medical data transmission is a major challenge in wireless communication to preserve their integrity and coherence. As the transmission takes place at high data rate, the complexity and throughput of the system, pertaining to the fetal ECG signal, is crucial. In addition to the accumulation of noises in the channel, the observation of fetal ECG signal, using diagnostic devices, also provides additive noise, thereby reducing the quality of the transmitted signal. The major motive of this paper is to demarcate the fetal ECG signal from noise at early stages of transmission using Chambolle-Pock based hybridized classifiers. This technique provides sensitivity of 91.1% followed by performance validation of Error Detection and correction adders for different decoder architectures in transceiver. Thereby area and power reduction of 86.3% and 91.1% is achieved. The simulations are carried out with MIT-BIH Arrhythmia using simulation tools, such as MATLAB 2013b, ModelSim 10.0b, and Cadence Virtuoso under 90 nm on over 200 data sets.

关键词： Additive noises decoder architectures Error detection and correction adders Evolution algorithms

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Fast INC-XOR codec for low-power address buses

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IET COMPUTERS AND DIGITAL TECHNIQUES 2007年第5期1卷 625-631页

作者： Parandeh-Afshar, H. Saneei, M. Afzali-Kusha, A. Pedram, M. Univ Tehran Sch Elect & Comp Engn Nanoelect Ctr Excellence Tehran Iran Univ So Calif Dept Elect Engn Syst Los Angeles CA 90089 USA

A very fast and low-power address bus encoder, whose critical path delay and area are only weakly dependent on the address bus width, is presented. Although the encoding algorithm of the proposed structure is the same as the INC-XOR encoding, its encoder and decoder architectures, called DX, are much faster. The DX architecture implements the INC-XOR encoding partially (partial DX architecture) or fully (registered DX architecture). The partial implementation, which is faster and consumes less power and silicon area, is appropriate for cases where the size of the basic block (sequential addresses without branches or jumps) is bounded, for example, by 256. The registered DX architecture uses a multi-stage pipelined structure with pseudo-incrementers to reduce the combinational delay of each pipeline stage. The two DX implementations (partial and registered) are compared with three conventional implementations of INC-XOR realised using the ripple carry, the carry look-ahead and Sklansky prefix incrementers. The results of the critical path delay, gate count, power-delay product and energy-delay product show considerable improvements over the conventional implementations.

关键词： partial DX architecture critical path delay Sklansky prefix incrementers power-delay product codecs energy-delay product multistage pipelined structure encoder architectures encoding registered DX architecture carry look-ahead incrementers logic gates ripple carry carry logic decoding pseudo-incrementers INC-XOR codec system buses low-power address bus encoder gate count decoder architectures

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Energy efficient VLSI decoder chip with reduced PAPR in FECG monitoring

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INTERNATIONAL JOURNAL OF ELECTRONICS 2020年第8期107卷 1304-1323页

作者： Preethi, D. Valarmathi, R. S. Harikumar, R. Bannari Amman Inst Technol Dept Elect & Commun Engn Erode India Vel Tech Rangarajan Dr Sagunthala R&D Inst Sci & Dept Elect & Commun Engn Chennai Tamil Nadu India

Medical data transmission is a major challenge in wireless communication to preserve their integrity and coherence. Orthogonal frequency division multiplexing (OFDM) has emerged as a modulation scheme that can achieve high data rates over frequency selective fading channel by multipath effects. As the foetal ECG (FECG) signal is large to process, the dimensionality of the data is reduced by linear discriminant analysis (LDA) and is then sent through the space time block coded (STBC) multiple input multiple output (MIMO) upon using cockroach swarm pptimisation algorithm as a classifier to demarcate the FECG signal from noise. This paper also proposes decoder design for STBC transmission over frequency-selective time-variant channels with data recovery at the receiver by using proposed error prediction and correction adders (EPD) to achieve reduced peak to average power ration (PAPR). The simulation results prove that the PAPR reduces by 1.3 dB and the sensitivity of classifier is 96.4%. The implementations are carried out over 200 data sets taken from MIT-BIH arrhythmia using simulation tools such as MATLAB 2013b, ModelSim 10.0b and Cadence Virtuoso under 65 nm. The finally fabricated and tested decoder chip consumes an average power of 0.64 mu W.

关键词： Additive noises Cockroach Swarm Optimisation decoder architectures error predictionand correction adders Peak to Average Power Ration

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Block-interlaced LDPC decoders with reduced interconnect complexity

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 2008年第1期55卷 74-78页

作者： Darabiha, Ahmad Carusone, Anthony Chan Kschischang, Frank R. Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Two design techniques are proposed for high-throughput low-density parity-check (LDPC) decoders. A broadcasting technique mitigates routing congestion by reducing the total global wirelength. An interlacing technique increases the decoder throughput by processing two consecutive frames simultaneously. The brief discusses how these techniques can be used for both fully parallel and partially parallel LDPC decoders. For fully parallel decoders with code lengths in the range of a few thousand bits, the half-broadcasting technique reduces the total global wirelength by about 26% without any hardware overhead. The block interlacing scheme is applied to the design of two fully parallel decoders, increasing the throughput by 60% and 71% at the cost of 5.5% and 9.5% gate count overhead, respectively.

关键词： 10-GB Ethernet channel coding decoder architectures iterative message-passing low-density parity-check (LDPC) codes very-large-scale integration (VLSI)

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A High Throughput and Low BER Implementation Method in TG Wireless Transmission System 9

A High Throughput and Low BER Implementation Method in TG Wi...

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9th IEEE Conference on Industrial Electronics and Applications (ICIEA)

作者： Wan, Guochun Yin, Guizhu Chen, Lan Zhanf, Qian Fan, Yongqing Tongji Univ Dept Elect Sci & Technol Shanghai 200092 Peoples R China Shanghai Inst Technol Sch Elect & Elect Engn Shanghai Peoples R China

ISBN: (纸本)9781479943159

Along with the development of high-speed railway, higher and higher technical requirements for the mobile communication system in it are raised. Communication Based Train Control (CBTC) will be based on mobile communication, of which the key problem is how to support high reliability of data transmission in order to improve utilization of tracks and enhance train's safety. The applications of LDPC in reliable high-speed data transmission which serves fault monitor and early-warning system in train-ground (TG) wireless communication are proposed. The design of high-throughput and complexity reduction for regular and irregular LDPC codes has been considered in decoding algorithm and architectural in order to accord with the performance of reliable train-ground information transmission. A parallel message updates and implement method are presented for LDPC decoder of train-ground system that bring negligible loss in performance compared to the ideal case. A new implement method which is designed of very large scale integration have been proposed in this paper. The LDPC decoder has been applied in reliable train-ground high throughput fault monitor and digital early-warning communication system. Testing result demonstrates that the proposed architecture achieves a throughput of 18.629Mbps, which meets the performance requirements of reliable high data transmission and higher throughout.

关键词： communication based on train control low density parity check codes reliable transmission decoder architectures

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Multi-mode message passing switch networks applied for QC-LDPC decoder

Multi-mode message passing switch networks applied for QC-LD...

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IEEE International Symposium on Circuits and Systems

作者： Liu, Chih-Hao Lin, Chien-Ching Chang, Hsie-Chia Lee, Chen-Yi Hsu, Yarsun Natl Tsing Hua Univ Dept Elect Engn 101Sec 2Kuang Fu Rd Hsinchu 30013 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9781424420780

The multi-mode message passing switch networks for multi-standard QC-LDPC decoder are presented. An enhanced self-routing switch network with only one barrel shifter permutation structure and a shifter-based two-way duplicated switch network are proposed to support 19 and 3 different submatrices defined in IEEE 802.16e and IEEE 802.11n. These proposed switch networks can route the decoding message in parallel by different sizes without signal congestion. The enhanced self-routing switch network can switch the messages at different expansion factors with the lowest hardware complexity. Under the condition of a smaller expansion factor, the decoder throughput can be enhanced from the two-way duplicated switch network by increasing the parallelism. In the 130nm CMOS synthesis result, the proposed enhanced self-routing and the two-way duplicated switch network gate counts are 21.9k and 37.4k at 384MHz operation frequency.

关键词： LDPC code decoder architectures quasi-cyclic IEEE 802.16e WiMax IEEE 802.11n switch network

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Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC decoders

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SENSORS 2022年第5期22卷 1792-1792页

作者： Nguyen, Tuy Tan Nguyen, Tram Thi Bao Lee, Hanho Inha Univ Dept Informat & Commun Engn Incheon 22212 South Korea

This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature.

关键词： 5G New Radio decoder architectures LDPC code switch network

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