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12th Conference on Electron Technology (ELTE)

作者： Wielgus, Andrzej Pleskacz, Witold Warsaw Univ Technol Inst Microelect & Optoelect Ul Koszykowa 75 PL-00662 Warsaw Poland

ISBN: (数字)9781510608443

ISBN: (纸本)9781510608436;9781510608443

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. It allows to estimate the probabilities of physical open defects occurrences in a cell, describes its faulty behavior caused by the defects and finds the test sequences that detect those faults. Finally, the minimal set of test sequences is selected to cover all detectable faults and the optimal complex test sequence is constructed. Experimental results for cells from industrial standard cell library are presented as well.

关键词： defect based testing full open test sequence standard cells characterization

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Resistive Shorts Characterization in CMOS Standard Cells for Test Pattern Generation

Resistive Shorts Characterization in CMOS Standard Cells for...

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11th Conference on Electron Technology

作者： Wielgus, Andrzej Potrykus, Bartosz Warsaw Univ Technol Inst Microelect & Optoelect PL-00662 Warsaw Poland

ISBN: (纸本)9780819495211

This paper presents an extended method of CMOS standard cells characterization for defect based voltage testing. Resistance of a short defect is taken into account while considering faulty behavior caused by this defect and finding the test vectors that detect this fault. Finally, all of found vectors are validated to check their effectiveness in fault covering and the optimal test sequence for all detectable faults is constructed. Experimental results for cells from industrial standard cell library are presented.

关键词： defect based testing resistive bridging faults standard cells characterization

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Genetic defect based March Test Generation for SRAM 1

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Conference on EvoApplications 2011: EvoCOMPLEX, EvoGAMES, EvoIASP, EvoINTELLIGENCE, EvoNUM, AND EvoSTOC

作者： Di Carlo, Stefano Politano, Gianfranco Prinetto, Paolo Savino, Alessandro Scionti, Alberto Politecn Torino Control & Comp Engn Dept I-10129 Turin Italy

ISBN: (数字)9783642205200

ISBN: (纸本)9783642205194

The continuos shrinking of semiconductor's nodes makes semiconductor memories increasingly prone to electrical defects tightly related to the internal structure of the memory. Exploring the effect of fabrication defects in future technologies, and identifying new classes of functional fault models with their corresponding test sequences, is a time consuming task up to now mainly performed by hand. This paper proposes a new approach to automate this procedure exploiting a dedicated genetic algorithm.

关键词： Memory testing march test generation defect based testing

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A Build-In Self-Test Technique for RF Mixers

A Build-In Self-Test Technique for RF Mixers

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13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems

作者： Dermentzoglou, Lambros Arapoyanni, Angela Tsiatouhas, Yiorgos Univ Athens Dept Informat & Telecommun Athens Greece Univ Ioannina Dept Comp Sci Ioannina Greece

ISBN: (纸本)9781424466139

A Build-In Self-Test (BiST) circuit suitable for embedded RF Mixers in System-on-Chip applications is presented in this paper. This is a defect-oriented test scheme that dynamically sets the Mixer to operate in homodyne mode. The DC level generated at its output is used to control the oscillation frequency of a simple voltage controlled oscillator. Deviations of the oscillation frequency from the expected range of values indicate a defective Mixer. The proposed BiST technique has been applied to a typical receiver's differential RF Mixer using a 0.35 mu m CMOS technology. Simulation results validated the efficiency of the BiST circuit which was capable to provide a high fault coverage of catastrophic faults (which exceeds 91%) and a small test application time (1 mu s), at a silicon area cost approximately 16% of the Mixer area.

关键词： Build-in-Self Test Design for Testability RF Mixer defect based testing

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On detection of bridge defects with stuck-at tests

On detection of bridge defects with stuck-at tests

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7th Workshop on RTL and High Level testing

作者： Miyase, Kohei Terashima, Kenta Wen, Xiaoqing Kajihara, Seiji Reddy, Sudhakar M. Univ Iowa Dept Elect & Comp Engn Iowa City IA 52242 USA Kyushu Inst Technol Fac Comp Sci & Syst Engn Iizuka Fukuoka 8208502 Japan

If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. In this paper we propose a method to detect bridge defects with a test set initially generated for stuck-at faults in a full scan sequential circuit. The proposed method doesn't add new test vectors to the test set but modifies test vectors. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND-type, OR-type and 4-way bridging faults, respectively. Experimental results show that the proposed method increases the defect coverage.

关键词： defect based testing test vector generation test vector modification bridging faults fault extraction

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Test challenges in nanometer technologies

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2001年第3-4期17卷 209-218页

作者： Kundu, S Zachariah, ST Sengupta, S Galivanche, R Intel Corp Santa Clara CA 95054 USA

Device scaling has led to the blurring of the boundary between design and test: marginalities introduced by design tool approximations can cause failures when aggressive designs are subjected to process variation. Larger die sizes are more vulnerable to intra-die variations, invalidating analyses based on a number of given process corners. These trends are eroding the predictability of test quality based on stuck-at fault coverage. Industry studies have shown that an at-speed functional test with poor stuck-at fault coverage can be a better DPM screen than a set of scan tests with very high stuck-at fault coverage. Contrary to conventional wisdom, we have observed that a high stuck-at fault test set is not necessarily good at detecting faults that model actual failure mechanisms. One approach to address the test quality crisis is to rethink the fault model that is at the core of these tests. Targeting realistic fault models is a challenge that spans the design, test and manufacturing domains: the extraction of realistic faults has to analyze the design at the physical and circuit levels of abstraction while taking into account the failure modes observed during manufacture. Practical fault models need to be defined that adequately model failing behavior while remaining amenable to automatic test generation. The addition of these fault models place increasing performance and capacity demands on already stressed test generation and fault simulation tools. A new generation of analysis and test generation tools is needed to address the challenge of defect-based test. We provide a detailed discussion of process technology trends that are responsible for next generation test problems, and present a test automation infrastructure being developed at Intel to meet the challenge.

关键词： defect based testing circuit marginality testing process marginality testing path delay testing

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Test challenges in nanometer technologies

Test challenges in nanometer technologies

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IEEE European Test Workshop

作者： Kundu, S Zachariah, ST Sengupta, S Galivanche, R Intel Corp Santa Clara CA 95054 USA

关键词： defect based testing circuit marginality testing process marginality testing path delay testing

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