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Detection and Localization of Channel-Short Faults in Regular On-Chip Interconnection Networks

SN Computer Science 2023年第5期4卷 1-18页

作者： Bhowmik, Biswajit Swami Vivekananda NoC Lab BRICS Lab Department of Computer Science and Engineering National Institute of Technology Karnataka Surathkal 575025 India

With the rapid developments in VLSI technology, the communication channels in networks-on-chip (NoCs) can place many wires for sustaining high-performance requirements over the communication bottleneck in multicore, multiprocessor systems-on-chip (MPSoCs). Consequently, NoC channels, due to increased wire density, are exposed to different logic level faults, e.g., short resulting in reliability and yield issues in NoC-based systems. These faults can appear at any stage of the lifetime of a chip. While existing in an NoC communication architecture, the channel-short faults bring the system into various failures that surprisingly cause a significant deviation from its expected performance. In this work, an online, distributed test solution is presented that detects and diagnoses intra-channel and inter-channel short faults and analyzes the effect of these faults on various performance metrics. Fault simulations ensure up to 100% coverage metrics. Network simulation shows insight into the impact of channel shorts in NoC performances. It is observed that the amount of test time is reduced to 10 × concerning a set of prior works while employed for a group of NoCs. It is also seen on these NoCs that average packet latency is improved by 15.14–46.79% while energy consumption is reduced by 13.68–39.13% by the current solution than the set of existing solutions. Moreover, the proposed solution scales to all NoCs irrespective of size, topology, and channel width at an acceptable test cost. © 2023, The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd.

关键词： defect-based testing Diagonal node selection Fault modelling and evaluation Intra-channel and inter-channel manufacturing shorts Model scalability Networks on a chip Performance analysis and measurement System level failures

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Profiting from Unit Tests For Integration testing 9

Profiting from Unit Tests For Integration Testing

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9th IEEE International Conference on Software testing, Verification and Validation (ICST)

作者： Holling, Dominik Hofbauer, Andreas Pretschner, Alexander Gemmar, Matthias Tech Univ Munich Garching Germany ITK Engn AG Rulzheim Germany

ISBN: (纸本)9781509018277

In practice, integration testing typically focuses on a small selection of components or subsystems to integrate and test. This reduces the effort required to create test cases and test environments. However, many defects are only detected when performing integration testing on all possible integrations. These defects are typically only detected later in the development process and lead to increased testing and fault localization efforts. By describing and operationalizing knowledge of such defects, we are able to (semi-) automatically detect them in integration testing. Our OUTFIT tool targets superfluous or missing functionality and untested exception/fault handling in Matlab Simulink models and generated code. It re-uses existing, or automatically generates, high coverage test cases to measure coverage in an opportunistically assembled integration of components or subsystems. A manual inspection of the coverage results then reveals missing or potentially superfluous behavior and thus reveals defects of the targeted kind. Used in a bottomup integration testing strategy, OUTFIT front loads the detection of such defects, and reduces the fault localization effort. We evaluate OUTFIT using three components of a real-world electrical engine control system of a hybrid car. We find that the results are reproducible, effective and efficiently produced. The achieved coverage of the results is reproducible for 10 executions within a small standard deviation. OUTFIT is effective in finding a potential defect, and efficiently analyzes all evaluated components within a worst case execution time of 110 minutes.

关键词： defect-based testing integration testing KLEE Matlab Simulink Symbolic Execution

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Layout-Oriented defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test 25

Layout-Oriented Defect Set Reduction for Fast Circuit Simula...

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25th IEEE Asian Test Symposium (ATS)

作者： Liu, Hsuan-Wei Lin, Bing-Yang Wu, Cheng-Wen Natl Tsing Hua Univ Dept Elect Engn Hsinchu 30013 Taiwan

ISBN: (纸本)9781509038091

The cell-aware test (CAT) methodology was previously proposed to target cell-internal faults that cannot be easily detected by gate-level stuck-at fault (SAF) patterns generated by conventional ATPG. It was shown to reduce the defect level on CMOS-based designs, with the help of detailed defect injected transistor-level circuit simulation and defect-enhanced SAF ATPG. The detailed transistor-level circuit simulation has been considered an issue in CAT, as it is very time consuming. The problem mainly lies in that all parasitic capacitors and resistors extracted from cell layout are considered as defect targets, so the defect set is large. To reduce the defect set, and therefore the circuit simulation time, we take layout into consideration when we construct the defect set for each cell, effectively removing the redundant or unnecessary defects and therefore reducing the circuit simulation time dramatically. We propose a generalized approach that can be used to build the fault models based on the cell layout, where the generated faults are closer to the realistic physical defects on the layout, so the number of faults is significantly reduced. The proposed method is verified by commercial 180nm and 350nm CMOS standard cell library, and the circuit simulation time is reduced to only 19% or even lower as compared with the original CAT methodology.

关键词： Automatic test pattern generation (ATPG) cell-aware test (CAT) circuit simulation defect-based testing fault modeling and simulation

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CΔIDDQ: Improving Current-based testing and Diagnosis Through Modified Test Pattern Generation

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2011年第1期19卷 130-141页

作者： Thibeault, Claude Hariri, Yassine Ecole Technol Super Dept Elect Engn Montreal PQ Canada

This paper presents a novel approach to extending the life of current-based test techniques for the detection and diagnosis of bridging defects. Called C Delta IDDQ (Complementary Delta IDDQ), this approach combines a modified test pattern generation with a simple post-processing of I(DDQ) measurements (namely additions and subtractions) such that the resulting measurement combination equals zero. Consequently, C Delta IDDQ eliminates the main current variance sources: wafer-to-wafer, IC-to-IC and vector-to-vector variations;the only remaining source is the measurement variance. The modified test pattern generation is based on the innovative concept of transient-fault test pattern decomposition and the use of layout information to target realistic bridging defect sites. Verification based on logic simulation confirms that the combination of the resulting subset of fault-free I(DDQ) measurements is equal to 0. Using this promising new technique, bridging defect detection capability can be improved by orders of magnitude. Simulation results also show that this improved detection capability may be necessary even for low-power devices.

关键词： ATPG bridging defects current testing current variance defect-based testing

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Optimizing program disturb fault tests using defect-based testing

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2005年第6期24卷 905-915页

作者： Mohammad, MG Saluja, KK Kuwait Univ Dept Comp Engn Khaldiyah 13060 Kuwait Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

Nonvolatile memories (NVMs) are susceptible to a special type of faults known as program disturb faults. These faults are described using logical fault models and often functional tests are used to detect different faults that occur under such models. The use of functional fault models and tests results in the simplification of the testing process, although such tests can be very long. In this paper, we present a defect-based model that can be used to model different disturb faults in NVM. The relationship between defect location and fault manifestation is first established using electrical simulation. Next, the use of stress tests and margin read schemes and how they are used to detect disturb faults is discussed. Using electrical simulation results, we show that defect-based testing can be used to optimize the cost of program disturb tests of NVM.

关键词： defect-based testing disturb faults electrical simulation flash memory margin read

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Experimental characterization of CMOS interconnect open defects

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第1期27卷 123-136页

作者： Arumi, Daniel Rodriguez-Montanes, Rosa Figueras, Joan Univ Politecn Cataluna Dept Elect Engn Barcelona 08028 Spain

Open defects have been intentionally designed in a set of interconnect metal lines. In order to improve the controllability and the observability of the experimental design, a simple bus structure with a scan register followed by a hold. register is used to manage the set of interconnect lines. The strength of the open defects has been varied within a. realistic range of resistances ranging from a full (complete) open to a weak (low resistance) open by means of broken metal lines and transmission gates, respectively. Experiments performed with an automatic test equipment show the influence of coupling capacitances with adjacent lines on the electrical behavior of the defective line. Furthermore, experimental evidence of the history effect on the delay caused by resistive opens is investigated. Validation of the measured results by means of theoretical as well as simulation analysis is presented. Finally, some recommendations to generate Stuck-at, I-DDQ, and delay test are discussed in order to improve the detectability of such defects.

关键词： defect-based testing detectability conditions open defects testability of opens

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defect detection using quiescent signal analysis

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2005年第5期21卷 463-483页

作者： Patel, C Singh, A Plusquellic, J Univ Maryland Baltimore Cty Dept CSEE Baltimore MD 21250 USA

I-DDQ or steady state current testing has been extensively used in the industry as a mainstream defect detection and reliability screen. The background leakage current has increased significantly with the advent of ultra deep submicron technologies. This increased background leakage noise makes it difficult to differentiate defect-free devices from those with defects that draw significantly small amount of currents. Therefore it is impossible to use single threshold I-DDQ testing for today's technologies. Several techniques that improve the resolution of I-DDQ testing have been proposed to replace the single threshold detection scheme. However, even these techniques are suffering from loss of resolution that is required for detection of subtle defects in the presence of leakage currents in excess of a few mA. All these techniques use a single I-DDQ measurement for detection and thus the scalability of these techniques is limited. Quiescent Signal Analysis (QSA) is a novel I-DDQ defect detection and diagnosis technique that uses I-DDQ measurements at multiple chip supply pads. Implicit in our methodology is a leakage calibration technique that scales the total leakage current over multiple simultaneous measurements. This helps in decreasing the background leakage component in individual measurements and thus increases the resolution of this technique to subtle defects. defect detection is accomplished by applying linear regression analysis to the multiple supply port measurements and using outlier analysis to identify defective devices. The effectiveness of this technique is demonstrated in this paper using simulation experiments on portion of a production power grid. Predicted chip size and leakage values from the International Technology Roadmap for semiconductors (ITRS) are used in these experiments. One of the other major concerns expressed in ITRS is that of significant increase in intra-die process variations. The performance of the proposed technique in presen

关键词： defect-based testing I-DDQ current testing parametric testing multiple current measurements Quiescent Signal Analysis

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Simulating realistic bridging and crosstalk faults in an industrial setting

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JOURNAL OF ELECTRONIC testing-THEORY AND APPLICATIONS 2003年第4期19卷 387-395页

作者： Bradford, J Delong, H Polian, I Becker, B Micronas GmbH D-79108 Freiburg Germany Univ Freiburg Inst Comp Sci D-79110 Freiburg Germany

Three different techniques for simulating realistic faults generated from IC layout are discussed. Two of them deal with bridging faults, and the third one handles crosstalk faults. The simulation is performed on top of a commercial simulator and thus is very well applicable in an industrial environment. No change of the design database and only minimal changes of the test shell are required. Experimental results are reported for a library cell and a block from a full-custom design.

关键词： fault simulation defect-based testing industrial experiences crosstalk

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The detection of defects in a niobium tri-layer process

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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2003年第2期13卷 95-98页

作者： Joseph, AA Heuvelmans, S Gerritsma, GJ Kerkhoff, HG Univ Twente MESA Testable Design & Testing Microsyst Grp NL-7500 AE Enschede Netherlands Univ Twente Inst Res NL-7500 AE Enschede Netherlands Univ Twente Low Temp Phys Grp NL-7500 AE Enschede Netherlands

Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 4190,000, the quality of the process has to be assured so as to realize these,complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed. test-structures for detection of the top-ranking defects, which will. be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designied, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.

关键词： defect-based testing PDM RSFQ circuit testing structural testing superconductor devices

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Simulating realistic bridging and crosstalk faults in an industrial setting 7

Simulating realistic bridging and crosstalk faults in an ind...

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7th IEEE European Test Workshop (ETW 02)

作者： Bradford, J Delong, H Polian, I Becker, B Micronas GmbH D-79108 Freiburg Germany Univ Freiburg Inst Comp Sci D-79110 Freiburg Germany

ISBN: (纸本)0769517153

关键词： fault simulation defect-based testing industrial experiences crosstalk

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