Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 4190,...
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Niobium (Nb) LTS processes are emerging as the technology for future ultra high-speed systems especially in the digital domain. As the number of Josephson Junctions (JJ) per chip has recently increased to around 4190,000, the quality of the process has to be assured so as to realize these,complex circuits. Until now, very little or no information is available in the literature on how to achieve this. In this paper we present an approach and results of a study conducted on an RSFQ process. Measurements and SEM inspection were carried out on sample chips and a list of possible defects has been identified and described in detail. We have also developed. test-structures for detection of the top-ranking defects, which will. be used for yield analysis and the determination of the probability distribution of faults in the process. A test chip has been designied, based on the results of this study, and certain types of defects were introduced in the design to study the behavior of faulty junctions and interconnections.
The detection of catastrophic short and open faults in bipolar current mode logic (CML) circuits is studied. The non-intrusive tests considered include functional (logic) tests, an Idd test, and a common-mode test. A ...
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The detection of catastrophic short and open faults in bipolar current mode logic (CML) circuits is studied. The non-intrusive tests considered include functional (logic) tests, an Idd test, and a common-mode test. A 622 Mbps SONET SIPO (Serial-In/Parallel-Out) and a PISO (Parallel-In/Serial-Out) circuit form the basis of this case study.
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